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  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/riscv64.s 

    	MULW	X5, X6, X7				// bb035302

	// 13.2: Division Operations
	DIV	X5, X6, X7				// b3435302
	DIVU	X5, X6, X7				// b3535302
	REM	X5, X6, X7				// b3635302
	REMU	X5, X6, X7				// b3735302
	DIVW	X5, X6, X7				// bb435302
	DIVUW	X5, X6, X7				// bb535302
	REMW	X5, X6, X7				// bb635302
	REMUW	X5, X6, X7				// bb735302

	// 14.2: Load-Reserved/Store-Conditional (Zalrsc)
	LRW	(X5), X6				// 2fa30214
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Sat Apr 04 05:25:40 GMT 2026
    - 74.2K bytes
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