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Results 1 - 10 of 13 for xmm5 (0.07 sec)

  1. src/cmd/vendor/golang.org/x/arch/x86/x86asm/gnu.go

    	M3:   "%mm3",
    	M4:   "%mm4",
    	M5:   "%mm5",
    	M6:   "%mm6",
    	M7:   "%mm7",
    	X0:   "%xmm0",
    	X1:   "%xmm1",
    	X2:   "%xmm2",
    	X3:   "%xmm3",
    	X4:   "%xmm4",
    	X5:   "%xmm5",
    	X6:   "%xmm6",
    	X7:   "%xmm7",
    	X8:   "%xmm8",
    	X9:   "%xmm9",
    	X10:  "%xmm10",
    	X11:  "%xmm11",
    	X12:  "%xmm12",
    	X13:  "%xmm13",
    	X14:  "%xmm14",
    	X15:  "%xmm15",
    	CS:   "%cs",
    	SS:   "%ss",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 21.4K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

    	// "VMOVQ r/m64, xmm1"/6E vs "VMOVQ xmm2/m64, xmm1"/7E with mem operand.
    	VMOVQ (AX), X20           // 62e1fd086e20 or 62e1fe087e20
    	VMOVQ 7(DX), X20          // 62e1fd086ea207000000 or 62e1fe087ea207000000
    	VMOVQ -15(R11)(CX*1), X20 // 62c1fd086ea40bf1ffffff or 62c1fe087ea40bf1ffffff
    	VMOVQ (SP)(AX*2), X20     // 62e1fd086e2444 or 62e1fe087e2444
    	// "VMOVQ xmm1, r/m64"/7E vs "VMOVQ xmm1, xmm2/m64"/D6 with mem operand.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 57.6K bytes
    - Viewed (0)
  3. src/cmd/vendor/golang.org/x/arch/x86/x86asm/decode.go

    	xArgXmm          // arg xmm
    	xArgXMM0         // arg <XMM0>
    	xArgXmm1         // arg xmm1
    	xArgXmm2         // arg xmm2
    	xArgXmm2M128     // arg xmm2/m128
    	xArgYmm2M256     // arg ymm2/m256
    	xArgXmm2M16      // arg xmm2/m16
    	xArgXmm2M32      // arg xmm2/m32
    	xArgXmm2M64      // arg xmm2/m64
    	xArgXmmM128      // arg xmm/m128
    	xArgXmmM32       // arg xmm/m32
    	xArgXmmM64       // arg xmm/m64
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 10 18:59:52 UTC 2023
    - 45.1K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm64/asm7.go

    			c.checkindex(p, index, 15)
    			Q = 1
    			imm5 = 1
    			imm5 |= index << 1
    		case ARNG_2D:
    			c.checkindex(p, index, 1)
    			Q = 1
    			imm5 = 8
    			imm5 |= index << 4
    		case ARNG_2S:
    			c.checkindex(p, index, 3)
    			Q = 0
    			imm5 = 4
    			imm5 |= index << 3
    		case ARNG_4H:
    			c.checkindex(p, index, 7)
    			Q = 0
    			imm5 = 2
    			imm5 |= index << 2
    		case ARNG_4S:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/lex/lex_test.go

    		"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n",
    	},
    	{
    		"nested multiline macro",
    		lines(
    			"#define KEYROUND(xmm, load, off, r1, r2, index) \\",
    			"\tMOVBLZX	(BP)(DX*4),	R8 \\",
    			"\tload((off+1), r2) \\",
    			"\tMOVB	R8,		(off*4)(R12) \\",
    			"\tPINSRW	$index, (BP)(R8*4), xmm",
    			"#define LOAD(off, reg) \\",
    			"\tMOVBLZX	(off*4)(R12),	reg \\",
    			"\tADDB	reg,		DX",
    			"KEYROUND(X0, LOAD, 8, AX, BX, 0)",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 29 07:48:38 UTC 2023
    - 5.8K bytes
    - Viewed (0)
  6. src/vendor/golang.org/x/sys/cpu/cpu_x86.go

    	X86.HasRDRAND = isSet(30, ecx1)
    
    	var osSupportsAVX, osSupportsAVX512 bool
    	// For XGETBV, OSXSAVE bit is required and sufficient.
    	if X86.HasOSXSAVE {
    		eax, _ := xgetbv()
    		// Check if XMM and YMM registers have OS support.
    		osSupportsAVX = isSet(1, eax) && isSet(2, eax)
    
    		if runtime.GOOS == "darwin" {
    			// Darwin doesn't save/restore AVX-512 mask registers correctly across signal handlers.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 4.9K bytes
    - Viewed (0)
  7. src/internal/cpu/cpu_x86.go

    	osSupportsAVX := false
    	osSupportsAVX512 := false
    	// For XGETBV, OSXSAVE bit is required and sufficient.
    	if X86.HasOSXSAVE {
    		eax, _ := xgetbv()
    		// Check if XMM and YMM registers have OS support.
    		osSupportsAVX = isSet(eax, 1<<1) && isSet(eax, 1<<2)
    
    		// AVX512 detection does not work on Darwin,
    		// see https://github.com/golang/go/issues/49233
    		//
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 13:40:20 UTC 2024
    - 5.8K bytes
    - Viewed (0)
  8. src/internal/chacha8rand/chacha8_amd64.s

    	SEED(1, SI, X5)
    	SEED(2, R8, X6)
    	SEED(3, R9, X7)
    	SEED(4, R10, X8)
    	SEED(5, R11, X9)
    	SEED(6, R12, X10)
    	SEED(7, R13, X11)
    
    	// Zeros for remaining two matrix entries.
    	// We have just enough XMM registers to hold the state,
    	// without one for the temporary, so we flush and restore
    	// some values to and from memory to provide a temporary.
    	// The initial temporary is X15, so zero its memory instead
    	// of X15 itself.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Dec 05 20:34:30 UTC 2023
    - 4.6K bytes
    - Viewed (0)
  9. src/runtime/sys_windows_amd64.s

    _0args:
    
    	// Call stdcall function.
    	CALL	AX
    
    	ADDQ	$(const_maxArgs*8), SP
    
    	// Return result.
    	MOVQ	0(SP), CX
    	MOVQ	8(SP), SP
    	MOVQ	AX, libcall_r1(CX)
    	// Floating point return values are returned in XMM0. Setting r2 to this
    	// value in case this call returned a floating point value. For details,
    	// see https://docs.microsoft.com/en-us/cpp/build/x64-calling-convention
    	MOVQ    X0, libcall_r2(CX)
    
    	// GetLastError().
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Feb 19 07:24:08 UTC 2024
    - 8.4K bytes
    - Viewed (0)
  10. src/cmd/vendor/golang.org/x/arch/x86/x86asm/inst.go

    	// 387 floating point registers.
    	F0
    	F1
    	F2
    	F3
    	F4
    	F5
    	F6
    	F7
    
    	// MMX registers.
    	M0
    	M1
    	M2
    	M3
    	M4
    	M5
    	M6
    	M7
    
    	// XMM registers.
    	X0
    	X1
    	X2
    	X3
    	X4
    	X5
    	X6
    	X7
    	X8
    	X9
    	X10
    	X11
    	X12
    	X13
    	X14
    	X15
    
    	// Segment registers.
    	ES
    	CS
    	SS
    	DS
    	FS
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 10.6K bytes
    - Viewed (0)
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