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Results 1 - 10 of 1,930 for nRules (0.26 sec)
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internal/event/rules.go
rulesCopy[pattern] = targetIDSet.Clone() } return rulesCopy } // Union - returns union with given rules as new rules. func (rules Rules) Union(rules2 Rules) Rules { nrules := rules.Clone() for pattern, targetIDSet := range rules2 { nrules[pattern] = nrules[pattern].Union(targetIDSet) } return nrules } // Difference - returns difference with given rules as new rules.
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri May 24 23:05:23 UTC 2024 - 2.7K bytes - Viewed (0) -
staging/src/k8s.io/apiserver/pkg/util/flowcontrol/gen_test.go
Spec: flowcontrol.FlowSchemaSpec{}} // 5% chance of zero rules, otherwise draw from 1--6 biased low nRules := (1 + rng.Intn(3)) * (1 + rng.Intn(2)) * ((19 + rng.Intn(20)) / 20) ftr := &fsTestingRecord{fs: fs, wellFormed: true, matchesAllResourceRequests: nRules > 0 && rng.Float32() < 0.1, matchesAllNonResourceRequests: nRules > 0 && rng.Float32() < 0.1, digests: map[bool]map[bool][]RequestDigest{
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Mon Oct 30 12:18:40 UTC 2023 - 24.8K bytes - Viewed (0) -
cmd/site-replication.go
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri May 24 23:05:23 UTC 2024 - 184.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64splitload.rules
// This file contains rules used by flagalloc and addressingmodes to // split a flag-generating merged load op into separate load and op. // Unlike with the other rules files, not all of these // rules will be applied to all values. // Rather, flagalloc will request for rules to be applied // to a particular problematic value. // These are often the exact inverse of rules in AMD64.rules, // only with the conditions removed. //
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Oct 04 19:35:46 UTC 2022 - 3.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules
// Copyright 2022 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This file contains rules used by the laterLower pass. // These are often the exact inverse of rules in ARM64.rules. (ADDconst [c] x) && !isARM64addcon(c) => (ADD x (MOVDconst [c])) (SUBconst [c] x) && !isARM64addcon(c) => (SUB x (MOVDconst [c]))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 4.1K bytes - Viewed (0) -
platforms/core-configuration/model-core/src/main/java/org/gradle/model/Rules.java
import java.lang.annotation.Target; /** * Denotes that the {@link RuleSource} method rule carrying this annotation defines additional rules based on its inputs. */ @Retention(RetentionPolicy.RUNTIME) @Target(ElementType.METHOD) @Incubating public @interface Rules {
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Thu Sep 28 09:51:04 UTC 2023 - 1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/386splitload.rules
// Copyright 2019 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // See the top of AMD64splitload.rules for discussion of these rules. (CMP(L|W|B)load {sym} [off] ptr x mem) => (CMP(L|W|B) (MOV(L|W|B)load {sym} [off] ptr mem) x) (CMPLconstload {sym} [vo] ptr mem) => (CMPLconst (MOVLload {sym} [vo.Off()] ptr mem) [vo.Val()])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Oct 04 19:35:46 UTC 2022 - 620 bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules
// Copyright 2022 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This file contains rules used by the laterLower pass. // Simplify ISEL x $0 z into ISELZ (ISEL [a] x (MOVDconst [0]) z) => (ISELZ [a] x z) // Simplify ISEL $0 y z into ISELZ by inverting comparison and reversing arguments. (ISEL [a] (MOVDconst [0]) y z) => (ISELZ [a^0x4] y z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 3.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules
the shift input. L6:(SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y) L7:(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y) L8:(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y) L9: L10:// See comments in ARM64latelower.rules for why these are here. L11:(MOVLQZX x) && zeroUpper32Bits(x,3) => x L12:(MOVWQZX x) && zeroUpper48Bits(x,3) => x L13:(MOVBQZX x) && zeroUpper56Bits(x,3) => x ...
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 636 bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/dec.rules
// Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This file contains rules to decompose builtin compound types // (complex,string,slice,interface) into their constituent // types. These rules work together with the decomposeBuiltIn // pass which handles phis of these types. (Store {t} _ _ mem) && t.Size() == 0 => mem // complex ops
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 00:48:31 UTC 2023 - 6.9K bytes - Viewed (0)