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Results 1 - 6 of 6 for mvcc (0.05 sec)

  1. .bazelrc

    build:cuda_clang_official --crosstool_top="@local_config_cuda//crosstool:toolchain"
    
    # Build with nvcc for CUDA and clang for host
    build:cuda_nvcc --config=cuda
    build:cuda_nvcc --action_env=TF_NVCC_CLANG="1"
    build:cuda_nvcc --@local_config_cuda//:cuda_compiler=nvcc
    # Old config for backward compatibility
    build:nvcc_clang --config=cuda_nvcc
    
    # Debug config
    build:dbg -c dbg
    Registered: Tue Nov 05 12:39:12 UTC 2024
    - Last Modified: Mon Oct 28 22:02:31 UTC 2024
    - 51.3K bytes
    - Viewed (0)
  2. configure.py

      Args:
        environ_cp: copy of the os.environ.
      """
      question = 'Do you want to use clang as CUDA compiler?'
      yes_reply = 'Clang will be used as CUDA compiler.'
      no_reply = 'nvcc will be used as CUDA compiler.'
      set_action_env_var(
          environ_cp,
          'TF_CUDA_CLANG',
          None,
          True,
          question=question,
          yes_reply=yes_reply,
          no_reply=no_reply,
    Registered: Tue Nov 05 12:39:12 UTC 2024
    - Last Modified: Wed Oct 02 22:16:02 UTC 2024
    - 48.2K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/s390x.s

    	NC	$8, (R15), n-8(SP)       // d407f010f000
    	OC	$8, (R15), n-8(SP)       // d607f010f000
    	MVC	$8, (R15), n-8(SP)       // d207f010f000
    	MVCIN	$8, (R15), n-8(SP)       // e807f010f000
    	CLC	$8, (R15), n-8(SP)       // d507f000f010
    	XC	$256, -8(R15), -8(R15)   // b90400afc2a8fffffff8d7ffa000a000
    	MVC	$256, 8192(R1), 8192(R2) // b90400a2c2a800002000b90400b1c2b800002000d2ffa000b000
    
    	CMP	R1, R2                 // b9200012
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 18 15:49:24 UTC 2024
    - 22.1K bytes
    - Viewed (0)
  4. tensorflow/BUILD

        name = "is_cuda_clang",
        match_all = [
            ":is_cuda_enabled",
            ":is_cuda_compiler_clang",
        ],
    )
    
    # Config setting that is satisfied when CUDA device code should be compiled
    # with nvcc. It does not imply that CUDA support has been enabled.
    alias(
        name = "is_cuda_compiler_nvcc",
        actual = if_oss(
            "@local_config_cuda//:is_cuda_compiler_nvcc",
            "@local_config_cuda//cuda:FALSE",
    Registered: Tue Nov 05 12:39:12 UTC 2024
    - Last Modified: Wed Oct 16 05:28:35 UTC 2024
    - 53.5K bytes
    - Viewed (0)
  5. doc/asm.html

    <code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at
    <code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively.
    </p>
    
    <p>
    Storage-and-storage instructions such as <code>MVC</code> and <code>XC</code> are written
    with the length as the first argument.
    For example, <code>XC</code> <code>$8,</code> <code>(R9),</code> <code>(R9)</code> would clear
    eight bytes at the address specified in <code>R9</code>.
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Nov 28 19:15:27 UTC 2023
    - 36.3K bytes
    - Viewed (0)
  6. RELEASE.md

    *   Fixes a heap OOB in `MirrorPadGrad` ([CVE-2022-41895](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-41895))
    *   Fixes a crash in `Mfcc` ([CVE-2022-41896](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-41896))
    *   Fixes a heap OOB in `FractionalMaxPoolGrad` ([CVE-2022-41897](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-41897))
    Registered: Tue Nov 05 12:39:12 UTC 2024
    - Last Modified: Tue Oct 22 14:33:53 UTC 2024
    - 735.3K bytes
    - Viewed (0)
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