// Test low-8 register for /is4 "hr" operand.
	VPBLENDVB X0, (BX), X1, X2              // c4e3714c1300
	// <XMM0>/Yxr0 tests.
	SHA256RNDS2 X0, (BX), X2   // 0f38cb13
	SHA256RNDS2 X0, (R11), X2  // 410f38cb13
	SHA256RNDS2 X0, X2, X2     // 0f38cbd2
	SHA256RNDS2 X0, X11, X2    // 410f38cbd3
	SHA256RNDS2 X0, (BX), X11  // 440f38cb1b
	SHA256RNDS2 X0, (R11), X11 // 450f38cb1b
	SHA256RNDS2 X0, X2, X11    // 440f38cbda

AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 32(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 48(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 64(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 80(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3...

	VMOVQ		-12(R4), V2.W4	// 82f42f30
	VMOVQ		(R4), V3.V2	// 83001030
	VMOVQ		24(R4), V3.V2	// 830c1030
	VMOVQ		-16(R4), V3.V2	// 83f81730
	XVMOVQ		(R4), X0.B32	// 80008032
	XVMOVQ		1(R4), X0.B32	// 80048032
	XVMOVQ		-5(R4), X0.B32	// 80ecbf32
	XVMOVQ		(R4), X1.H16	// 81004032
	XVMOVQ		2(R4), X1.H16	// 81044032
	XVMOVQ		-10(R4), X1.H16	// 81ec5f32
	XVMOVQ		(R4), X2.W8	// 82002032

func ARMMRCOffset(op obj.As, cond string, x0, x1, x2, x3, x4, x5 int64) (offset int64, op0 obj.As, ok bool) {
	op1 := int64(0)
	if op == arm.AMRC {
		op1 = 1
	}
	bits, ok := ParseARMCondition(cond)
	if !ok {
		return
	}
	offset = (0xe << 24) | // opcode
		(op1 << 20) | // MCR/MRC
		((int64(bits) ^ arm.C_SCOND_XOR) << 28) | // scond
		((x0 & 15) << 8) | //coprocessor number

pkg p1, var SIVal SI
pkg p1, var StrConv string
pkg p1, var V string
pkg p1, var V1 uint64
pkg p1, var V2 p2.Twoer
pkg p1, var VError //deprecated
pkg p1, var VError Error
pkg p1, var X I
pkg p1, var X0 int64

			prog.To.Type = obj.TYPE_CONST
			x0 := p.getConstant(prog, op, &a[0])
			x1 := p.getConstant(prog, op, &a[1])
			x2 := int64(p.getRegister(prog, op, &a[2]))
			x3 := int64(p.getRegister(prog, op, &a[3]))
			x4 := int64(p.getRegister(prog, op, &a[4]))
			x5 := p.getConstant(prog, op, &a[5])
			// Cond is handled specially for this instruction.
			offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5)
			if !ok {