Search Options

Display Count
Sort
Preferred Language
Advanced Search

Results 1 - 10 of 20 for X0 (0.04 seconds)

  1. src/cmd/asm/internal/asm/testdata/riscv64validation.s

    	CJR	X0					// ERROR "cannot use register X0 in rs1"
    	CJR	X10, X11				// ERROR "expected no register in rs2"
    	CJALR	X0					// ERROR "cannot use register X0 in rs1"
    	CJALR	X10, X11				// ERROR "expected no register in rd"
    	CBEQZ	X5, 1(PC)				// ERROR "expected integer prime register in rs1"
    	CBNEZ	X5, 1(PC)				// ERROR "expected integer prime register in rs1"
    	CLI	$3, X0					// ERROR "cannot use register X0 in rd"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Nov 13 12:17:37 GMT 2025
    - 42.1K bytes
    - Click Count (0)
  2. src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

    	// Test low-8 register for /is4 "hr" operand.
    	VPBLENDVB X0, (BX), X1, X2              // c4e3714c1300
    	// <XMM0>/Yxr0 tests.
    	SHA256RNDS2 X0, (BX), X2   // 0f38cb13
    	SHA256RNDS2 X0, (R11), X2  // 410f38cb13
    	SHA256RNDS2 X0, X2, X2     // 0f38cbd2
    	SHA256RNDS2 X0, X11, X2    // 410f38cbd3
    	SHA256RNDS2 X0, (BX), X11  // 440f38cb1b
    	SHA256RNDS2 X0, (R11), X11 // 450f38cb1b
    	SHA256RNDS2 X0, X2, X11    // 440f38cbda
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Feb 20 11:20:03 GMT 2025
    - 57.7K bytes
    - Click Count (0)
  3. lib/fips140/v1.26.0.zip

    AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 32(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 48(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 64(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 80(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3...
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Jan 08 17:58:32 GMT 2026
    - 660.3K bytes
    - Click Count (0)
  4. cmd/erasure-decode_test.go

    	const size = 12 * 1024 * 1024
    	b.Run(" 00|00 ", func(b *testing.B) { benchmarkErasureDecode(2, 2, 0, 0, size, b) })
    	b.Run(" 00|X0 ", func(b *testing.B) { benchmarkErasureDecode(2, 2, 0, 1, size, b) })
    	b.Run(" X0|00 ", func(b *testing.B) { benchmarkErasureDecode(2, 2, 1, 0, size, b) })
    	b.Run(" X0|X0 ", func(b *testing.B) { benchmarkErasureDecode(2, 2, 1, 1, size, b) })
    }
    
    func BenchmarkErasureDecode_4_64KB(b *testing.B) {
    Created: Sun Apr 05 19:28:12 GMT 2026
    - Last Modified: Fri Aug 29 02:39:48 GMT 2025
    - 21K bytes
    - Click Count (0)
  5. lib/fips140/v1.0.0-c2097c7c.zip

    AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 32(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 48(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 64(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 80(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3...
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Sep 25 19:53:19 GMT 2025
    - 642.7K bytes
    - Click Count (0)
  6. cmd/erasure-encode_test.go

    	b.Run(" 00|X0 ", func(b *testing.B) { benchmarkErasureEncode(2, 2, 0, 1, size, b) })
    	b.Run(" X0|00 ", func(b *testing.B) { benchmarkErasureEncode(2, 2, 1, 0, size, b) })
    }
    
    func BenchmarkErasureEncode_4_64KB(b *testing.B) {
    	const size = 64 * 1024
    	b.Run(" 00|00 ", func(b *testing.B) { benchmarkErasureEncode(2, 2, 0, 0, size, b) })
    Created: Sun Apr 05 19:28:12 GMT 2026
    - Last Modified: Fri Aug 29 02:39:48 GMT 2025
    - 11.8K bytes
    - Click Count (0)
  7. src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s

    	RET
    TEXT ·a28(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	PEXTRD $0, X0, R15
    	ADDQ $1, R15
    	RET
    TEXT ·a29(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	VPEXTRD $0, X0, R15
    	ADDQ $1, R15
    	RET
    TEXT ·a30(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Nov 20 19:05:03 GMT 2025
    - 4.9K bytes
    - Click Count (0)
  8. src/cmd/asm/internal/asm/testdata/riscv64error.s

    // license that can be found in the LICENSE file.
    
    TEXT errors(SB),$0
    	CSRRC	(X10), CYCLE, X5		// ERROR "integer register or immediate expected for 1st operand"
    	CSRRC	X0, TU, X5			// ERROR "unknown CSR"
    	CSRRC	X0, CYCLE			// ERROR "missing CSR name"
    	CSRRC	X0, CYCLE, (X10)		// ERROR "needs an integer register output"
    	CSRRC	$-1, TIME, X15			// ERROR "immediate out of range 0 to 31"
    	CSRRCI	$32, TIME, X15			// ERROR "immediate out of range 0 to 31"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Wed Apr 01 04:17:57 GMT 2026
    - 27.2K bytes
    - Click Count (0)
  9. android/guava-tests/test/com/google/common/hash/FarmHashFingerprint64Test.java

          h ^= fingerprint(buf, bufLen);
          h = remix(h);
          buf[bufLen++] = getChar(h);
    
          int x0 = buf[bufLen - 1] & 0xff;
          int x1 = buf[bufLen - 2] & 0xff;
          int x2 = buf[bufLen - 3] & 0xff;
          int x3 = buf[bufLen / 2] & 0xff;
          buf[((x0 << 16) + (x1 << 8) + x2) % bufLen] ^= x3;
          buf[((x1 << 16) + (x2 << 8) + x3) % bufLen] ^= i % 256;
        }
    Created: Fri Apr 03 12:43:13 GMT 2026
    - Last Modified: Thu Mar 19 18:53:45 GMT 2026
    - 6.4K bytes
    - Click Count (0)
  10. src/cmd/asm/internal/arch/arm.go

    func ARMMRCOffset(op obj.As, cond string, x0, x1, x2, x3, x4, x5 int64) (offset int64, op0 obj.As, ok bool) {
    	op1 := int64(0)
    	if op == arm.AMRC {
    		op1 = 1
    	}
    	bits, ok := ParseARMCondition(cond)
    	if !ok {
    		return
    	}
    	offset = (0xe << 24) | // opcode
    		(op1 << 20) | // MCR/MRC
    		((int64(bits) ^ arm.C_SCOND_XOR) << 28) | // scond
    		((x0 & 15) << 8) | //coprocessor number
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Wed Oct 23 15:18:14 GMT 2024
    - 6.1K bytes
    - Click Count (0)
Back to Top