LDADDALW	R5, (R6), RSP                            // ERROR "illegal combination"
	LDADDALH	R5, (R6), RSP                            // ERROR "illegal combination"
	LDADDALB	R5, (R6), RSP                            // ERROR "illegal combination"
	LDADDD	R5, (R6), RSP                                    // ERROR "illegal combination"
	LDADDW	R5, (R6), RSP                                    // ERROR "illegal combination"

	RLWNM $3, R4, $29, $31, R6      // 54861f7e
	RLWNM $0, R4, $29, $31, R6      // 5486077e
	RLWNM R0, R4, $29, $31, R6      // 5c86077e
	RLWNM R3, R4, $7, R6            // 5c861f7e
	RLWNM R3, R4, $29, $31, R6      // 5c861f7e
	RLWNMCC $3, R4, $7, R6          // 54861f7f
	RLWNMCC $3, R4, $29, $31, R6    // 54861f7f
	RLWNMCC R3, R4, $7, R6          // 5c861f7f
	RLWNMCC R3, R4, $29, $31, R6    // 5c861f7f
	RLDMI $0, R4, $7, R6            // 7886076c

// SRL
	SRL	$0, R5, R6           // 0560a0e1
	SRL	$1, R5, R6           // a560a0e1
	SRL	$14, R5, R6          // 2567a0e1
	SRL	$15, R5, R6          // a567a0e1
	SRL	$30, R5, R6          // 256fa0e1
	SRL	$31, R5, R6          // a56fa0e1
	SRL	$32, R5, R6          // 2560a0e1
	SRL.S	$14, R5, R6          // 2567b0e1
	SRL.S	$15, R5, R6          // a567b0e1
	SRL.S	$30, R5, R6          // 256fb0e1

	CLC	$8, (R15), n-8(SP)       // d507f000f010
	XC	$256, -8(R15), -8(R15)   // b90400afc2a8fffffff8d7ffa000a000
	MVCLE   0, R4, R6                // a8640000
	MVCLE   4095, R4, R6             // a8640fff
	MVCLE   $4095, R4, R6            // a8640fff
	MVCLE   (R3), R4, R6             // a8643000
	MVCLE   10(R3), R4, R6           // a864300a

	CMP	R1, R2                 // b9200012
	CMP	R3, $32767             // a73f7fff

	LDADDLD	R5, (R6), ZR                         // df0065f8
	LDADDLW	R5, (R6), ZR                         // df0065b8
	LDADDLH	R5, (R6), ZR                         // df006578
	LDADDLB	R5, (R6), ZR                         // df006538
	LDCLRD	R5, (R6), ZR                         // df1025f8
	LDCLRW	R5, (R6), ZR                         // df1025b8
	LDCLRH	R5, (R6), ZR                         // df102578

	SRLV	R4, R5, R6 		// a6101900
	SRLV	$4, R4, R5		// 85104500
	SRLV	$4, R4			// 84104500
	SRLV	$32, R4, R5 		// 85804500
	SRLV	$32, R4			// 84804500

	MASKEQZ	R4, R5, R6		// a6101300
	MASKNEZ	R4, R5, R6		// a6901300

	// CRC32
	CRCWBW	R4, R5, R6		// a6102400
	CRCWHW	R4, R5, R6		// a6902400
	CRCWWW	R4, R5, R6		// a6102500
	CRCWVW	R4, R5, R6		// a6902500
	CRCCWBW	R4, R5, R6		// a6102600

	MOVWF	F6, F8                                    // c68ab8ee
	MOVWF	R6, F8                                    // 106b0feecf8ab8ee
	MOVWF.U	F6, F8                                    // 468ab8ee
	MOVWF.U	R6, F8                                    // 106b0fee4f8ab8ee
	MOVWD	F6, F8                                    // c68bb8ee
	MOVWD	R6, F8                                    // 106b0feecf8bb8ee

	MOVW.S	R3, CPSR           // ERROR "invalid .S suffix"
	MOVW.S	$0, CPSR           // ERROR "invalid .S suffix"
	MOVM.S	(R0), [R2-R4]      // ERROR "invalid .S suffix"
	MOVM.S	[R1-R6], (R9)      // ERROR "invalid .S suffix"
	SWPW.S	R1, (R2), R3       // ERROR "invalid .S suffix"
	MOVF.S	(R0), F1           // ERROR "invalid .S suffix"
	MOVF.S	F9, (R4)           // ERROR "invalid .S suffix"

to a <code>NOP</code> instruction).
</p>

<p>
Addressing modes:
</p>

<ul>

<li>
<code>(R5)(R6*1)</code>: The location at <code>R5</code> plus <code>R6</code>.
It is a scaled mode as on the x86, but the only scale allowed is <code>1</code>.
</li>

</ul>

<h3 id="mips">MIPS, MIPS64</h3>

<p>

sure it's zero MOVD $0, R4 // c = 0 MOVD R5, R12 AND $-2, R12 CMPBGE R5, $2, A6 BR E6 A6: MOVD (R8)(R1*1), R6 MULHDU R9, R6 MOVD (R2)(R1*1), R10 ADDC R10, R11 // add to low order bits ADDE R0, R6 ADDC R4, R11 ADDE R0, R6 MOVD R6, R4 MOVD R11, (R2)(R1*1) MOVD (8)(R8)(R1*1), R6 MULHDU R9, R6 MOVD (8)(R2)(R1*1), R10 ADDC R10, R11 // add to low order bits ADDE R0, R6 ADDC R4, R11 ADDE R0, R6 MOVD R6, R4 MOVD R11, (8)(R2)(R1*1) ADD $16, R1 // i*8 + 8 ADD $2, R7 // i++ CMPBLT R7, R12, A6 BR E6 L6: // TODO:...