- Sort Score
- Num 10 results
- Language All
Results 1 - 9 of 9 for R11 (0.08 seconds)
-
lib/fips140/v1.26.0.zip
BSWAPL R11 MOVL R11, 188(SP) MOVOU X11, 192(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 204(SP) MOVOU X11, 208(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 220(SP) MOVOU X11, 224(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 236(SP) MOVOU X11, 240(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 252(SP) MOVOU 128(SP), X0 MOVOU 144(SP), X1 MOVOU 160(SP), X2 MOVOU 176(SP), X3 MOVOU 192(SP), X4 MOVOU 208(SP), X5 MOVOU...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Jan 08 17:58:32 GMT 2026 - 660.3K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Feb 24 21:29:25 GMT 2026 - 44K bytes - Click Count (0) -
lib/fips140/v1.0.0-c2097c7c.zip
BSWAPL R11 MOVL R11, 188(SP) MOVOU X11, 192(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 204(SP) MOVOU X11, 208(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 220(SP) MOVOU X11, 224(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 236(SP) MOVOU X11, 240(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 252(SP) MOVOU 128(SP), X0 MOVOU 144(SP), X1 MOVOU 160(SP), X2 MOVOU 176(SP), X3 MOVOU 192(SP), X4 MOVOU 208(SP), X5 MOVOU...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Sep 25 19:53:19 GMT 2025 - 642.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
SHA1MSG1 (BX), X2 // 0f38c913 SHA1MSG1 (R11), X2 // 410f38c913 SHA1MSG1 X2, X2 // 0f38c9d2 SHA1MSG1 X11, X2 // 410f38c9d3 SHA1MSG1 (BX), X11 // 440f38c91b SHA1MSG1 (R11), X11 // 450f38c91b SHA1MSG1 X2, X11 // 440f38c9da SHA1MSG1 X11, X11 // 450f38c9db SHA1MSG2 (BX), X2 // 0f38ca13 SHA1MSG2 (R11), X2 // 410f38ca13 SHA1MSG2 X2, X2 // 0f38cad2
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Feb 20 11:20:03 GMT 2025 - 57.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Feb 27 20:41:17 GMT 2026 - 96.2K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
LAA R1, R2, 524287(R3) // eb213fff7ff8 LAAG R4, R5, -524288(R6) // eb54600080e8 LAAL R7, R8, 8192(R9) // eb87900002fa LAALG R10, R11, -8192(R12) // ebbac000feea LAN R1, R2, (R3) // eb21300000f4 LANG R4, R5, (R6) // eb54600000e4 LAX R7, R8, (R9) // eb87900000f7 LAXG R10, R11, (R12) // ebbac00000e7 LAO R1, R2, (R3) // eb21300000f6
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Wed Jul 30 19:29:15 GMT 2025 - 22.9K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/armv6.s
SQRTF F0, F1 // c01ab1ee SQRTD F4, F5 // c45bb1ee MOVFD F0, F1 // c01ab7ee MOVDF F4, F5 // c45bb7ee LDREX (R8), R9 // 9f9f98e1 LDREXB (R11), R12 // 9fcfdbe1 LDREXD (R11), R12 // 9fcfbbe1 STREX R3, (R4), R5 // STREX (R4), R3, R5 // 935f84e1 STREXB R8, (R9), g // STREXB (R9), R8, g // 98afc9e1 STREXD R8, (R9), g // STREXD (R9), R8, g // 98afa9e1
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Wed Oct 23 15:18:14 GMT 2024 - 4.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Feb 24 21:29:25 GMT 2026 - 38.5K bytes - Click Count (0) -
doc/asm.html
that may not be expressible using a single hardware instruction. It implements these forms as multiple instructions, often using the <code>R11</code> register to hold temporary values. Hand-written assembly can use <code>R11</code>, but doing so requires being sure that the linker is not also using it to implement any of the other instructions in the function. </p> <p>
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Nov 14 19:09:46 GMT 2025 - 36.5K bytes - Click Count (0)