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src/cmd/asm/internal/asm/testdata/riscv64validation.s
CFSD F11, -1(X10) // ERROR "must be in range [0, 255]" CFSD F11, 36(X10) // ERROR "must be a multiple of 8" CFSD F11, 256(X10) // ERROR "must be in range [0, 255]" CJR X0 // ERROR "cannot use register X0 in rs1" CJR X10, X11 // ERROR "expected no register in rs2" CJALR X0 // ERROR "cannot use register X0 in rs1" CJALR X10, X11 // ERROR "expected no register in rd"
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Nov 13 12:17:37 GMT 2025 - 42.1K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
CFLD 32(X10), F11 // 0c31 CSW X11, 20(X10) // 4cc9 CSD X11, 24(X10) // 0ced CFSD F11, 32(X10) // 0cb1 // 26.4: Compressed Control Transfer Instructions CJ 1(PC) // 09a0 CJR X5 // 8282 CJALR X5 // 8292 CBEQZ X10, 1(PC) // 09c1 CBNEZ X10, 1(PC) // 09e1 // 26.5.1: Compressed Integer Constant-Generation Instructions CLI $-32, X5 // 8152 CLI $31, X5 // fd42
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Sat Apr 04 05:25:40 GMT 2026 - 74.2K bytes - Click Count (0)