// CLWB instructions:
	CLWB BX                          // ERROR "invalid instruction"
	// CLDEMOTE instructions:
	CLDEMOTE BX                      // ERROR "invalid instruction"
	// WAITPKG instructions:
	TPAUSE (BX)                      // ERROR "invalid instruction"
	UMONITOR (BX)                    // ERROR "invalid instruction"
	UMWAIT (BX)                      // ERROR "invalid instruction"

	{"(BP)(DX*4)", "(BP)(DX*4)"},
	{"(BP)(R8*4)", "(BP)(R8*4)"},
	{"(BX)", "(BX)"},
	{"(DI)", "(DI)"},
	{"(DI)(BX*1)", "(DI)(BX*1)"},
	{"(DX)", "(DX)"},
	{"(R9)", "(R9)"},
	{"(R9)(BX*8)", "(R9)(BX*8)"},
	{"(SI)", "(SI)"},
	{"(SI)(BX*1)", "(SI)(BX*1)"},
	{"(SI)(DX*1)", "(SI)(DX*1)"},
	{"(SP)", "(SP)"},
	{"(SP)(AX*4)", "(SP)(AX*4)"},
	{"32(SP)(BX*2)", "32(SP)(BX*2)"},
	{"32323(SP)(R8*4)", "32323(SP)(R8*4)"},

			"\tPINSRW	$index, (BP)(R8*4), xmm",
			"#define LOAD(off, reg) \\",
			"\tMOVBLZX	(off*4)(R12),	reg \\",
			"\tADDB	reg,		DX",
			"KEYROUND(X0, LOAD, 8, AX, BX, 0)",
		),
		"\n.MOVBLZX.(.BP.).(.DX.*.4.).,.R8.\n.\n.MOVBLZX.(.(.8.+.1.).*.4.).(.R12.).,.BX.\n.ADDB.BX.,.DX.\n.MOVB.R8.,.(.8.*.4.).(.R12.).\n.PINSRW.$.0.,.(.BP.).(.R8.*.4.).,.X0.\n",
	},
	{
		"taken #ifdef",
		lines(
			"#define A",
			"#ifdef A",

	// Zevex_rm_v_r.
	VADDPD Z2, Z9, Z21 // 62e1b54858ea
	VADDPD Z21, Z2, Z9 // 6231ed4858cd
	VADDPD Z9, Z21, Z2 // 62d1d54058d1

	CLWB (BX) // 660fae33
	CLDEMOTE (BX) // 0f1c03
	TPAUSE BX // 660faef3
	UMONITOR BX // f30faef3
	UMWAIT BX // f20faef3

	RDPID DX                                // f30fc7fa
	RDPID R11                               // f3410fc7fb

	// End of tests.

TEXT ·a14(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ R15, AX, BX // ERROR "when dynamic linking, R15 is clobbered by a global variable access and is used here"
	RET
TEXT ·a15(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ AX, R15, BX
	ADDQ $1, R15
	RET
TEXT ·a16(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ AX, BX, R15
	ADDQ $1, R15
	RET
TEXT ·a17(SB), 0, $0-0

	// Included to simplify validation of CL that fixed that.
	MOVQ (AX), M0  // 0f6f00
	MOVQ M0, 8(SP) // 0f7f442408
	MOVQ 8(SP), M0 // 0f6f442408
	MOVQ M0, (AX)  // 0f7f00
	MOVQ M0, (BX)  // 0f7f03
	// On non-64bit arch, Go asm allowed uint32 offsets instead of int32.
	// These tests check that property for backwards-compatibility.
	MOVL 2147483648(AX), AX  // 8b8000000080
	MOVL -2147483648(AX), AX // 8b8000000080

get_tls(CX)
MOVL	g(CX), AX     // Move g into AX.
MOVL	g_m(AX), BX   // Move g.m into BX.
</pre>

<p>
The <code>get_tls</code> macro is also defined on <a href="#amd64">amd64</a>.
</p>

<p>
Addressing modes:
</p>

<ul>

<li>
<code>(DI)(BX*2)</code>: The location at address <code>DI</code> plus <code>BX*2</code>.
</li>

<li>

	"DBW": arm.C_WBIT | arm.C_PBIT,
	"DAW": arm.C_WBIT,
	"IB":  arm.C_PBIT | arm.C_UBIT,
	"IA":  arm.C_UBIT,
	"DB":  arm.C_PBIT,
	"DA":  0,
}

var armJump = map[string]bool{
	"B":    true,
	"BL":   true,
	"BX":   true,
	"BEQ":  true,
	"BNE":  true,
	"BCS":  true,
	"BHS":  true,
	"BCC":  true,
	"BLO":  true,
	"BMI":  true,
	"BPL":  true,
	"BVS":  true,
	"BVC":  true,
	"BHI":  true,
	"BLS":  true,

//	{
//		outcode($1, $2, &nullgen, 0, &$4);
//	}
	BEQ	2(PC)
	B	foo(SB) // JMP foo(SB)
	BEQ	2(PC)
	B	bar<>(SB) // JMP bar<>(SB)

//
// BX
//
//	LTYPEBX comma ireg
//	{
//		outcode($1, Always, &nullgen, 0, &$3);
//	}
	BX	(R0)

//
// BEQ
//
//	LTYPE5 comma rel
//	{
//		outcode($1, Always, &nullgen, 0, &$3);
//	}
	BEQ	1(PC)

//
// SWI
//

buffer-from@^1.0.0:
  version "1.1.2"
  resolved "https://registry.yarnpkg.com/buffer-from/-/buffer-from-1.1.2.tgz#2b146a6fd72e80b4f55d255f35ed59a3a9a41bd5"
  integrity sha512-E+XQCRwSbaaiChtv6k6Dwgc+bx+Bs6vuKJHHl5kox/BaKbhiXzqQOwK4cO22yElGp2OCmjwVhT3HmxgyPGnJfQ==

bytes@3.1.2:
  version "3.1.2"
  resolved "https://registry.yarnpkg.com/bytes/-/bytes-3.1.2.tgz#8b0beeb98605adf1b128fa4386403c009e0221a5"