//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
// For range of 4 elements, Intel manual uses "+3" notation, for example:
//
//	VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128
//
// Given asm line:
//
//	VP4DPWSSDS Z5, [Z10-Z13], (AX)
//
// zmm2 is Z10, and Z13 is the only valid value for it (Z10+3).
// Only simple ranges are accepted, like [Z0-Z3].

H.lo路H^2.lo VPMSUMD IN1, H2L, XL1 // H^2.lo路H^2.lo VPMSUMD IN, H2, XM // H.hi路H^2.lo+H.lo路H^2.hi VPMSUMD IN1, H2, XM1 // H^2.hi路H^2.lo+H^2.lo路H^2.hi VPMSUMD IN, H2H, XH // H.hi路H^2.hi VPMSUMD IN1, H2H, XH1 // H^2.hi路H^2.hi VPMSUMD XL, XC2, T2 // 1st reduction phase VPMSUMD XL1, XC2, HH // 1st reduction phase VSLDOI $8, XM, ZERO, T0 VSLDOI $8, ZERO, XM, T1 VSLDOI $8, XM1, ZERO, HL VSLDOI $8, ZERO, XM1, H VXOR XL, T0, XL VXOR XH, T1, XH VXOR XL1, HL, XL1 VXOR XH1, H, XH1 VSLDOI $8, XL, XL, XL VSLDOI $8, XL1,...

H.lo路H^2.lo VPMSUMD IN1, H2L, XL1 // H^2.lo路H^2.lo VPMSUMD IN, H2, XM // H.hi路H^2.lo+H.lo路H^2.hi VPMSUMD IN1, H2, XM1 // H^2.hi路H^2.lo+H^2.lo路H^2.hi VPMSUMD IN, H2H, XH // H.hi路H^2.hi VPMSUMD IN1, H2H, XH1 // H^2.hi路H^2.hi VPMSUMD XL, XC2, T2 // 1st reduction phase VPMSUMD XL1, XC2, HH // 1st reduction phase VSLDOI $8, XM, ZERO, T0 VSLDOI $8, ZERO, XM, T1 VSLDOI $8, XM1, ZERO, HL VSLDOI $8, ZERO, XM1, H VXOR XL, T0, XL VXOR XH, T1, XH VXOR XL1, HL, XL1 VXOR XH1, H, XH1 VSLDOI $8, XL, XL, XL VSLDOI $8, XL1,...