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Results 1 - 9 of 9 for r6 (0.06 seconds)

  1. src/cmd/asm/internal/asm/testdata/arm64error.s

    	LDADDALW	R5, (R6), RSP                            // ERROR "illegal combination"
    	LDADDALH	R5, (R6), RSP                            // ERROR "illegal combination"
    	LDADDALB	R5, (R6), RSP                            // ERROR "illegal combination"
    	LDADDD	R5, (R6), RSP                                    // ERROR "illegal combination"
    	LDADDW	R5, (R6), RSP                                    // ERROR "illegal combination"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Tue Feb 24 21:29:25 GMT 2026
    - 38.5K bytes
    - Click Count (0)
  2. src/cmd/asm/internal/asm/testdata/arm64.s

    	LDADDLD	R5, (R6), ZR                         // df0065f8
    	LDADDLW	R5, (R6), ZR                         // df0065b8
    	LDADDLH	R5, (R6), ZR                         // df006578
    	LDADDLB	R5, (R6), ZR                         // df006538
    	LDCLRD	R5, (R6), ZR                         // df1025f8
    	LDCLRW	R5, (R6), ZR                         // df1025b8
    	LDCLRH	R5, (R6), ZR                         // df102578
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Feb 27 20:41:17 GMT 2026
    - 96.2K bytes
    - Click Count (0)
  3. src/cmd/asm/internal/asm/testdata/s390x.s

    	CLC	$8, (R15), n-8(SP)       // d507f000f010
    	XC	$256, -8(R15), -8(R15)   // b90400afc2a8fffffff8d7ffa000a000
    	MVCLE   0, R4, R6                // a8640000
    	MVCLE   4095, R4, R6             // a8640fff
    	MVCLE   $4095, R4, R6            // a8640fff
    	MVCLE   (R3), R4, R6             // a8643000
    	MVCLE   10(R3), R4, R6           // a864300a
    
    	CMP	R1, R2                 // b9200012
    	CMP	R3, $32767             // a73f7fff
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Wed Jul 30 19:29:15 GMT 2025
    - 22.9K bytes
    - Click Count (0)
  4. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	MULWVW	R4, R5, R6		// a6101f00
    	MULWVWU	R4, R5			// a5901f00
    	MULWVWU	R4, R5, R6		// a6901f00
    
    	MASKEQZ	R4, R5, R6		// a6101300
    	MASKNEZ	R4, R5, R6		// a6901300
    
    	// CRC32
    	CRCWBW	R4, R5, R6		// a6102400
    	CRCWHW	R4, R5, R6		// a6902400
    	CRCWWW	R4, R5, R6		// a6102500
    	CRCWVW	R4, R5, R6		// a6902500
    	CRCCWBW	R4, R5, R6		// a6102600
    	CRCCWHW	R4, R5, R6		// a6902600
    	CRCCWWW	R4, R5, R6		// a6102700
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Nov 27 00:46:52 GMT 2025
    - 44.5K bytes
    - Click Count (0)
  5. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	SUBSW R2.SXTH<<3, R13, R6                  // a6ad226b
    	SUBS R21.UXTX<<2, R27, R4                  // 646b35eb
    	SUBSW $(44<<12), R6, R9                    // SUBSW $180224, R6, R9         // c9b04071
    	SUBS $(1804<<12), R13, R9                  // SUBS $7389184, R13, R9        // a9315cf1
    	SUBSW R22->28, R6, R7                      // c770966b
    	SUBSW R22>>28, R6, R7                      // c770566b
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Tue Feb 24 21:29:25 GMT 2026
    - 44K bytes
    - Click Count (0)
  6. lib/fips140/v1.26.0.zip

    dst+0(FP), R4 MOVV a+8(FP), R5 MOVV b+16(FP), R6 MOVV n+24(FP), R7 SMALL_TAIL xor_256_lasx_check: SGTU $256, R7, R8 BNE R8, xor_128_lasx_check xor_256_lasx_loop: SUBV $256, R7 XVMOVQ (R5), X0 XVMOVQ 32(R5), X1 XVMOVQ 64(R5), X2 XVMOVQ 96(R5), X3 XVMOVQ 128(R5), X4 XVMOVQ 160(R5), X5 XVMOVQ 192(R5), X6 XVMOVQ 224(R5), X7 XVMOVQ (R6), X8 XVMOVQ 32(R6), X9 XVMOVQ 64(R6), X10 XVMOVQ 96(R6), X11 XVMOVQ 128(R6), X12 XVMOVQ 160(R6), X13 XVMOVQ 192(R6), X14 XVMOVQ 224(R6), X15 XVXORV X0, X8, X8 XVXORV X1, X9, X9...
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Jan 08 17:58:32 GMT 2026
    - 660.3K bytes
    - Click Count (0)
  7. doc/asm.html

    to a <code>NOP</code> instruction).
    </p>
    
    <p>
    Addressing modes:
    </p>
    
    <ul>
    
    <li>
    <code>(R5)(R6*1)</code>: The location at <code>R5</code> plus <code>R6</code>.
    It is a scaled mode as on the x86, but the only scale allowed is <code>1</code>.
    </li>
    
    </ul>
    
    <h3 id="mips">MIPS, MIPS64</h3>
    
    <p>
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Nov 14 19:09:46 GMT 2025
    - 36.5K bytes
    - Click Count (0)
  8. lib/fips140/v1.0.0-c2097c7c.zip

    sure it's zero MOVD $0, R4 // c = 0 MOVD R5, R12 AND $-2, R12 CMPBGE R5, $2, A6 BR E6 A6: MOVD (R8)(R1*1), R6 MULHDU R9, R6 MOVD (R2)(R1*1), R10 ADDC R10, R11 // add to low order bits ADDE R0, R6 ADDC R4, R11 ADDE R0, R6 MOVD R6, R4 MOVD R11, (R2)(R1*1) MOVD (8)(R8)(R1*1), R6 MULHDU R9, R6 MOVD (8)(R2)(R1*1), R10 ADDC R10, R11 // add to low order bits ADDE R0, R6 ADDC R4, R11 ADDE R0, R6 MOVD R6, R4 MOVD R11, (8)(R2)(R1*1) ADD $16, R1 // i*8 + 8 ADD $2, R7 // i++ CMPBLT R7, R12, A6 BR E6 L6: // TODO:...
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Sep 25 19:53:19 GMT 2025
    - 642.7K bytes
    - Click Count (0)
  9. src/test/java/org/codelibs/fess/suggest/entity/SuggestItemBoundaryTest.java

            String[] text = { "word1", "word2", "word3" };
            String[][] readings = { { "r1", "r2", "r3" }, // 3 readings
                    { "r4" }, // 1 reading
                    { "r5", "r6" } // 2 readings
            };
    
            SuggestItem item = new SuggestItem(text, readings, null, 0L, 0L, 1.0f, null, null, null, SuggestItem.Kind.QUERY);
    
            assertEquals(3, item.getReadings()[0].length);
    Created: Fri Apr 17 09:08:13 GMT 2026
    - Last Modified: Sat Jan 17 05:10:37 GMT 2026
    - 22.2K bytes
    - Click Count (0)
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