absl::Span<AbstractTensorHandle*> outputs) {
  Tape tape(/*persistent=*/false);
  tape.Watch(inputs[0]);
  AbstractTensorHandle* neg_output;
  TF_RETURN_IF_ERROR(ops::Neg(ctx, inputs[0], &neg_output, "Neg"));
  tape.RecordOperation(inputs, {neg_output}, nullptr, "Neg");
  return tape.ComputeGradient(ctx,
                              /*targets=*/{neg_output},
                              /*sources=*/inputs,

  // Add another oper to the graph.
  TF_Operation* neg = Neg(add, graph, s, "neg");
  ASSERT_EQ(TF_OK, TF_GetCode(s)) << TF_Message(s);

  NodeDef node_def_neg;
  ASSERT_TRUE(GetNodeDef(neg, &node_def_neg));
  EXPECT_EQ(string("add"), node_def_neg.input(0));

  // update edge of neg
  TF_UpdateEdge(graph, TF_Output{one, 0}, TF_Input{neg, 0}, s);

  ASSERT_TRUE(GetNodeDef(neg, &node_def_neg));

	case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPO, ppc64.AFCMPU:
		return true
	}
	return false
}

// IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is
// one of the NEG-like instructions that require special handling.
func IsPPC64NEG(op obj.As) bool {
	switch op {
	case ppc64.AADDMECC, ppc64.AADDMEVCC, ppc64.AADDMEV, ppc64.AADDME,
		ppc64.AADDZECC, ppc64.AADDZEVCC, ppc64.AADDZEV, ppc64.AADDZE,

	MOVB	X5, tls(SB)				// b70f00009b8f0f00b38f4f0023805f00

	// NOT pseudo-instruction
	NOT	X5					// 93c2f2ff
	NOT	X5, X6					// 13c3f2ff

	// NEG/NEGW pseudo-instructions
	NEG	X5					// b3025040
	NEG	X5, X6					// 33035040
	NEGW	X5					// bb025040
	NEGW	X5, X6					// 3b035040

	// This jumps to the second instruction in the function (the

	MODDU	R7, R8, R9            // a7a90000b90400b8b98700a7b904009a
	MODWU	R1, R2                // a7a90000b90400b2b99700a1b904002a
	MODWU	R1, R2, R3            // a7a90000b90400b2b99700a1b904003a
	NEG	R1                    // b9030011
	NEG	R1, R2                // b9030021
	NEGW	R1                    // b9130011
	NEGW	R1, R2                // b9130021
	FLOGR	R2, R2                // b9830022
	POPCNT	R3, R4                // b9e10043

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	CNTTZW R3,R4                    // 7c640434
	CNTTZWCC R3,R4                  // 7c640435
	CNTTZD R3,R4                    // 7c640474
	CNTTZDCC R3,R4                  // 7c640475
	NEG R3, R4                      // 7c8300d0
	NEGCC R3, R4                    // 7c8300d1
	NEGV R3, R4                     // 7c8304d0
	NEGVCC R3, R4                   // 7c8304d1

	BEQ 0(PC)                       // 41820000

	CMN	R7@>2, R5                                        // ERROR "unsupported shift operator"
	CMNW	R7@>2, R5                                        // ERROR "unsupported shift operator"
	NEG	R7@>2, R5                                        // ERROR "unsupported shift operator"
	NEGW	R7@>2, R5                                        // ERROR "unsupported shift operator"

			// prog.From is no address.
			prog.To = a[0]
		} else {
			prog.From = a[0]
			// prog.To is no address.
		}
		if p.arch.Family == sys.PPC64 && arch.IsPPC64NEG(op) {
			// NEG: From and To are both a[0].
			prog.To = a[0]
			prog.From = a[0]
			break
		}
	case 2:
		if p.arch.Family == sys.ARM {
			if arch.IsARMCMP(op) {
				prog.From = a[0]