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Results 1 - 10 of 10 for divdeuo (0.19 sec)

  1. src/cmd/internal/obj/ppc64/anames.go

    	"FSQRTSCC",
    	"CNTLZD",
    	"CNTLZDCC",
    	"CMPW",
    	"CMPWU",
    	"CMPB",
    	"FTDIV",
    	"FTSQRT",
    	"DIVD",
    	"DIVDCC",
    	"DIVDE",
    	"DIVDECC",
    	"DIVDEU",
    	"DIVDEUCC",
    	"DIVDVCC",
    	"DIVDV",
    	"DIVDU",
    	"DIVDUCC",
    	"DIVDUVCC",
    	"DIVDUV",
    	"EXTSW",
    	"EXTSWCC",
    	"FCFID",
    	"FCFIDCC",
    	"FCFIDU",
    	"FCFIDUCC",
    	"FCFIDS",
    	"FCFIDSCC",
    	"FCTID",
    	"FCTIDCC",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/ppc64.s

    	DIVWVCC R3, R4, R5              // 7ca41fd7
    	DIVDUV R3, R4, R5               // 7ca41f92
    	DIVDUVCC R3, R4, R5             // 7ca41f93
    	DIVWUVCC R3, R4, R5             // 7ca41f97
    	DIVWUV   R3, R4, R5             // 7ca41f96
    	DIVDE R3, R4, R5                // 7ca41b52
    	DIVDECC R3, R4, R5              // 7ca41b53
    	DIVDEU R3, R4, R5               // 7ca41b12
    	DIVDEUCC R3, R4, R5             // 7ca41b13
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/s390x.s

    	DIVD	R1, R2, R3            // b90400b2b90d00a1b904003b
    	DIVW	R4, R5                // b90400b5b91d00a4b904005b
    	DIVW	R4, R5, R6            // b90400b5b91d00a4b904006b
    	DIVDU	R7, R8                // a7a90000b90400b8b98700a7b904008b
    	DIVDU	R7, R8, R9            // a7a90000b90400b8b98700a7b904009b
    	DIVWU	R1, R2                // a7a90000b90400b2b99700a1b904002b
    	DIVWU	R1, R2, R3            // a7a90000b90400b2b99700a1b904003b
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 22 03:55:32 UTC 2023
    - 21.6K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/ppc64/a.out.go

    	AFSQRTCC
    	AFSQRTS
    	AFSQRTSCC
    
    	/* 64-bit */
    
    	ACNTLZD
    	ACNTLZDCC
    	ACMPW /* CMP with L=0 */
    	ACMPWU
    	ACMPB
    	AFTDIV
    	AFTSQRT
    	ADIVD
    	ADIVDCC
    	ADIVDE
    	ADIVDECC
    	ADIVDEU
    	ADIVDEUCC
    	ADIVDVCC
    	ADIVDV
    	ADIVDU
    	ADIVDUCC
    	ADIVDUVCC
    	ADIVDUV
    	AEXTSW
    	AEXTSWCC
    	/* AFCFIW; AFCFIWCC */
    	AFCFID
    	AFCFIDCC
    	AFCFIDU
    	AFCFIDUCC
    	AFCFIDS
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 16K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)
    		{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},   // arg0/arg1 (signed 32-bit)
    		{name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU", typ: "Int64"}, // arg0/arg1 (unsigned 64-bit)
    		{name: "DIVWU", argLength: 2, reg: gp21, asm: "DIVWU", typ: "Int32"}, // arg0/arg1 (unsigned 32-bit)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y)
    (Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y)))
    (Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y)
    (Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y)))
    (Mod32 x y) && buildcfg.GOPPC64 >= 9 => (MODSW x y)
    (Mod32 x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVW x y)))
    (Mod32u x y) && buildcfg.GOPPC64 >= 9 => (MODUW x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/ppc64/asm9.go

    			opset(AMULHDU, r0)
    			opset(AMULHDUCC, r0)
    			opset(AMULLDCC, r0)
    			opset(AMULLDVCC, r0)
    			opset(AMULLDV, r0)
    			opset(ADIVD, r0)
    			opset(ADIVDCC, r0)
    			opset(ADIVDE, r0)
    			opset(ADIVDEU, r0)
    			opset(ADIVDECC, r0)
    			opset(ADIVDEUCC, r0)
    			opset(ADIVDVCC, r0)
    			opset(ADIVDV, r0)
    			opset(ADIVDU, r0)
    			opset(ADIVDUV, r0)
    			opset(ADIVDUVCC, r0)
    			opset(ADIVDUCC, r0)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (Mul(32|16|8) ...) => (MULLW ...)
    (Mul32F ...) => (FMULS ...)
    (Mul64F ...) => (FMUL ...)
    (Mul64uhilo ...) => (MLGR ...)
    
    (Div32F ...) => (FDIVS ...)
    (Div64F ...) => (FDIV ...)
    
    (Div64 x y) => (DIVD x y)
    (Div64u ...) => (DIVDU ...)
    // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
    // so a sign/zero extension of the dividend is required.
    (Div32  x y) => (DIVW  (MOVWreg x) y)
    (Div32u x y) => (DIVWU (MOVWZreg x) y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewritePPC64.go

    		if !(buildcfg.GOPPC64 >= 9) {
    			break
    		}
    		v.reset(OpPPC64MODUD)
    		v.AddArg2(x, y)
    		return true
    	}
    	// match: (Mod64u x y)
    	// cond: buildcfg.GOPPC64 <= 8
    	// result: (SUB x (MULLD y (DIVDU x y)))
    	for {
    		x := v_0
    		y := v_1
    		if !(buildcfg.GOPPC64 <= 8) {
    			break
    		}
    		v.reset(OpPPC64SUB)
    		v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
    			},
    		},
    	},
    	{
    		name:   "DIVDU",
    		argLen: 2,
    		asm:    ppc64.ADIVDU,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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