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guava-tests/test/com/google/common/hash/BloomFilterTest.java
BloomFilter<Integer> bf2 = BloomFilter.create(Funnels.integerFunnel(), 100); bf2.put(element2); assertFalse(bf2.mightContain(element1)); assertTrue(bf2.mightContain(element2)); assertTrue(bf1.isCompatible(bf2)); bf1.putAll(bf2); assertTrue(bf1.mightContain(element1)); assertTrue(bf1.mightContain(element2)); assertFalse(bf2.mightContain(element1));
Registered: Wed Jun 12 16:38:11 UTC 2024 - Last Modified: Fri May 17 15:27:58 UTC 2024 - 21.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(MOVBUreg (UBFX [bfc] x)) && bfc.getARM64BFwidth() <= 8 => (UBFX [bfc] x) // ubfiz/ubfx combinations: merge shifts into bitfield ops (SRLconst [sc] (UBFX [bfc] x)) && sc < bfc.getARM64BFwidth() => (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) (UBFX [bfc] (SRLconst [sc] x)) && sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (UBFX [bfc] (SLLconst [sc] x)) // cond: sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
test/checkbce.go
j := i & 34 useInt(a[j]) j = i & 17 useInt(a[j]) } func f2b(a [35]int, i uint16) { useInt(a[i]) // ERROR "Found IsInBounds$" j := i & 34 useInt(a[j]) j = i & 17 useInt(a[j]) } func f2c(a [35]int, i uint32) { useInt(a[i]) // ERROR "Found IsInBounds$" j := i & 34 useInt(a[j]) j = i & 17 useInt(a[j]) } func f3(a [256]int, i uint8) { useInt(a[i]) useInt(a[i+10]) useInt(a[i+14])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:25 UTC 2023 - 3.7K bytes - Viewed (0) -
test/codegen/arithmetic.go
// amd64:"ANDL\t[$]1023" // arm64:"AND\t[$]1023",-"SDIV" // arm/6:"AND",-".*udiv" // arm/7:"BFC",-".*udiv",-"AND" // ppc64x:"RLDICL" return len(a) % 1024 } func LenMod2(s string) int { // 386:"ANDL\t[$]2047" // amd64:"ANDL\t[$]2047" // arm64:"AND\t[$]2047",-"SDIV" // arm/6:"AND",-".*udiv" // arm/7:"BFC",-".*udiv",-"AND" // ppc64x:"RLDICL" return len(s) % (4097 >> 1) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
guava/src/com/google/common/hash/BloomFilter.java
Registered: Wed Jun 12 16:38:11 UTC 2024 - Last Modified: Mon Apr 01 16:15:01 UTC 2024 - 26.3K bytes - Viewed (0) -
test/codegen/bits.go
} func and_mask_2(a uint64) uint64 { // arm64:`AND\t` return a & (1 << 63) } func and_mask_3(a, b uint32) (uint32, uint32) { // arm/7:`BIC`,-`AND` a &= 0xffffaaaa // arm/7:`BFC`,-`AND`,-`BIC` b &= 0xffc003ff return a, b } // Check generation of arm64 BIC/EON/ORN instructions func op_bic(x, y uint32) uint32 { // arm64:`BIC\t`,-`AND` return x &^ y }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 7.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
} // returns the lsb part of the auxInt field of arm64 bitfield ops. func (bfc arm64BitField) getARM64BFlsb() int64 { return int64(uint64(bfc) >> 8) } // returns the width part of the auxInt field of arm64 bitfield ops. func (bfc arm64BitField) getARM64BFwidth() int64 { return int64(bfc) & 0xff } // checks if mask >> rshift applied at lsb is a valid arm64 bitfield op mask.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
SWI $65535 // ffff00ef SWI // 000000ef // BFX/BFXU/BFC/BFI BFX $16, $8, R1, R2 // BFX $16, R1, $8, R2 // 5124afe7 BFX $29, $2, R8 // 5881bce7 BFXU $16, $8, R1, R2 // BFXU $16, R1, $8, R2 // 5124efe7 BFXU $29, $2, R8 // 5881fce7 BFC $29, $2, R8 // 1f81dee7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
r := int(p.Reg) o1 |= (uint32(rf)&15)<<8 | (uint32(r)&15)<<0 | (uint32(rt)&15)<<16 | (uint32(rt2)&15)<<12 case 18: /* BFX/BFXU/BFC/BFI */ o1 = c.oprrr(p, p.As, int(p.Scond)) rt := int(p.To.Reg) r := int(p.Reg) if r == 0 { r = rt } else if p.As == ABFC { // only "BFC $width, $lsb, Reg" is accepted, p.Reg must be 0 c.ctxt.Diag("illegal combination: %v", p) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0)