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src/cmd/asm/internal/asm/testdata/riscv64.s
AMOSWAPW X5, (X6), X7 // af23530e AMOSWAPD X5, (X6), X7 // af33530e AMOADDW X5, (X6), X7 // af235306 AMOADDD X5, (X6), X7 // af335306 AMOANDW X5, (X6), X7 // af235366 AMOANDD X5, (X6), X7 // af335366 AMOORW X5, (X6), X7 // af235346 AMOORD X5, (X6), X7 // af335346 AMOXORW X5, (X6), X7 // af235326 AMOXORD X5, (X6), X7 // af335326 AMOMAXW X5, (X6), X7 // af2353a6
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Nov 13 12:17:37 GMT 2025 - 73.7K bytes - Click Count (0) -
lib/fips140/v1.1.0-rc1.zip
X1 PXOR X11, X2 PXOR X12, X3 PXOR X13, X4 PXOR X14, X5 // Similarly if zero == 0 PCMPEQL X9, X9 MOVOU X7, X15 PANDN X9, X15 MOVOU 96(SP), X9 MOVOU 112(SP), X10 MOVOU 128(SP), X11 MOVOU 144(SP), X12 MOVOU p256one<>+0(SB), X13 MOVOU p256one<>+16(SB), X14 PAND X15, X0 PAND X15, X1 PAND X15, X2 PAND X15, X3 PAND X15, X4 PAND X15, X5 PAND X7, X9 PAND X7, X10 PAND X7, X11 PAND X7, X12 PAND X7, X13 PAND X7, X14 PXOR X9, X0 PXOR X10, X1 PXOR X11, X2 PXOR X12, X3 PXOR X13, X4 PXOR X14, X5 // Finally output...
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Dec 11 16:27:41 GMT 2025 - 663K bytes - Click Count (0) -
lib/fips140/v1.0.0-c2097c7c.zip
X1 PXOR X11, X2 PXOR X12, X3 PXOR X13, X4 PXOR X14, X5 // Similarly if zero == 0 PCMPEQL X9, X9 MOVOU X7, X15 PANDN X9, X15 MOVOU 96(SP), X9 MOVOU 112(SP), X10 MOVOU 128(SP), X11 MOVOU 144(SP), X12 MOVOU p256one<>+0(SB), X13 MOVOU p256one<>+16(SB), X14 PAND X15, X0 PAND X15, X1 PAND X15, X2 PAND X15, X3 PAND X15, X4 PAND X15, X5 PAND X7, X9 PAND X7, X10 PAND X7, X11 PAND X7, X12 PAND X7, X13 PAND X7, X14 PXOR X9, X0 PXOR X10, X1 PXOR X11, X2 PXOR X12, X3 PXOR X13, X4 PXOR X14, X5 // Finally output...
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Sep 25 19:53:19 GMT 2025 - 642.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64validation.s
CMV X0, X5 // ERROR "cannot use register X0 in rs2" CMV X5, X6, X7 // ERROR "expected no register in rs1" CMV X5, X0 // ERROR "cannot use register X0 in rd" CMV F1, X5 // ERROR "expected integer register in rs2" CMV X5, F1 // ERROR "expected integer register in rd" CADD X5, X6, X7 // ERROR "rd must be the same as rs1" CADD X0, X8 // ERROR "cannot use register X0 in rs2"
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Nov 13 12:17:37 GMT 2025 - 42.1K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
XVMOVQ X5, -2040(R4) // 8520e02c XVMOVQ X6, y+16(FP) // 0660c02c XVMOVQ X7, x+2030(FP) // 07d8df2c XVMOVQ (R4), X2 // 8200802c XVMOVQ 3(R4), X3 // 830c802c XVMOVQ 2044(R4), X4 // 84f09f2c XVMOVQ -2044(R4), X5 // 8510a02c XVMOVQ y+16(FP), X6 // 0660802c XVMOVQ x+2030(FP), X7 // 07d89f2c // Move vector element to general-purpose register: VMOVQ <Vn>.<T>[index], Rd
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Nov 27 00:46:52 GMT 2025 - 44.5K bytes - Click Count (0)