ADD	X9, X22, X9	// z_hi[0] = x[0] * y + z[0]
	ADD	X21, X29, X10	// z_lo[0] = x[0] * y + z[0] + c
	SLTU	X21, X10, X22
	ADD	X9, X22, X29	// next c

	MULHU	X11, X6, X12	// z_hi[1] = x[1] * y
	MUL	X11, X6, X11	// z_lo[1] = x[1] * y
	ADD	X11, X13, X21	// z_lo[1] = x[1] * y + z[1]
	SLTU	X11, X21, X22
	ADD	X12, X22, X12	// z_hi[1] = x[1] * y + z[1]
	ADD	X21, X29, X13	// z_lo[1] = x[1] * y + z[1] + c
	SLTU	X21, X13, X22

#define MSGSCHEDULE0(index) \
	MOVBU	((index*8)+0)(X29), X5; \
	MOVBU	((index*8)+1)(X29), X6; \
	MOVBU	((index*8)+2)(X29), X7; \
	MOVBU	((index*8)+3)(X29), X8; \
	SLL	$56, X5; \
	SLL	$48, X6; \
	OR	X5, X6, X5; \
	SLL	$40, X7; \
	OR	X5, X7, X5; \
	SLL	$32, X8; \
	OR	X5, X8, X5; \
	MOVBU	((index*8)+4)(X29), X9; \
	MOVBU	((index*8)+5)(X29), X6; \
	MOVBU	((index*8)+6)(X29), X7; \
	MOVBU	((index*8)+7)(X29), X8; \

	MOVBU	6(X10), X25
	MOVBU	7(X10), X29
	MOVBU	0(X12), X9
	MOVBU	1(X12), X16
	MOVBU	2(X12), X18
	MOVBU	3(X12), X20
	MOVBU	4(X12), X22
	MOVBU	5(X12), X24
	MOVBU	6(X12), X28
	MOVBU	7(X12), X30
	BNE	X8, X9, cmp1a
	BNE	X15, X16, cmp1b
	BNE	X17, X18, cmp1c
	BNE	X19, X20, cmp1d
	BNE	X21, X22, cmp1e
	BNE	X23, X24, cmp1f
	BNE	X25, X28, cmp1g
	BNE	X29, X30, cmp1h
	ADD	$8, X10
	ADD	$8, X12

	CPOP	X22, X23				// 931b2b60
	CPOPW	X23, X24				// 1b9c2b60
	CTZ	X24, X25				// 931c1c60
	CTZW	X25, X26				// 1b9d1c60
	MAX	X26, X28, X29				// b36eae0b
	MAX	X26, X28				// 336eae0b
	MAXU	X28, X29, X30				// 33ffce0b
	MAXU	X28, X29				// b3fece0b
	MIN	X29, X30, X5				// b342df0b
	MIN	X29, X30				// 334fdf0b
	MINU	X30, X5, X6				// 33d3e20b
	MINU	X30, X5					// b3d2e20b
	ORN	X6, X7, X8				// 33e46340

	MOV X17, 104(X2)
	MOV X18, 112(X2)
	MOV X19, 120(X2)
	MOV X20, 128(X2)
	MOV X21, 136(X2)
	MOV X22, 144(X2)
	MOV X23, 152(X2)
	MOV X24, 160(X2)
	MOV X25, 168(X2)
	MOV X26, 176(X2)
	MOV X28, 184(X2)
	MOV X29, 192(X2)
	MOV X30, 200(X2)
	MOVD F0, 208(X2)
	MOVD F1, 216(X2)
	MOVD F2, 224(X2)
	MOVD F3, 232(X2)
	MOVD F4, 240(X2)
	MOVD F5, 248(X2)
	MOVD F6, 256(X2)
	MOVD F7, 264(X2)
	MOVD F8, 272(X2)

				{2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},

	var x20 [10<<20]byte
	var x21 [10<<20]byte
	var x22 [10<<20]byte
	var x23 [10<<20]byte
	var x24 [10<<20]byte
	var x25 [10<<20]byte
	var x26 [10<<20]byte
	var x27 [10<<20]byte
	var x28 [10<<20]byte
	var x29 [10<<20]byte
	var x30 [10<<20]byte
	var x31 [10<<20]byte
	var x32 [10<<20]byte
	var x33 [10<<20]byte
	var x34 [10<<20]byte
	var x35 [10<<20]byte
	var x36 [10<<20]byte
	var x37 [10<<20]byte
	var x38 [10<<20]byte

	},
	{
		"tobe;LSB;7",
		"TOBEORNOTTOBEORTOBEORNOT",
		"\x54\x4f\x42\x45\x4f\x52\x4e\x4f\x54\x82\x84\x86\x8b\x85\x87\x89\x81",
		nil,
	},
	{
		"tobe;LSB;8",
		"TOBEORNOTTOBEORTOBEORNOT",
		"\x54\x9e\x08\x29\xf2\x44\x8a\x93\x27\x54\x04\x12\x34\xb8\xb0\xe0\xc1\x84\x01\x01",
		nil,
	},
	{
		"tobe;MSB;7",
		"TOBEORNOTTOBEORTOBEORNOT",
		"\x54\x4f\x42\x45\x4f\x52\x4e\x4f\x54\x82\x84\x86\x8b\x85\x87\x89\x81",
		nil,
	},

	esr uint32 // exception syndrome
	exc uint32 // number of arm exception taken
}

type regs64 struct {
	x     [29]uint64 // registers x0 to x28
	fp    uint64     // frame register, x29
	lr    uint64     // link register, x30
	sp    uint64     // stack pointer, x31
	pc    uint64     // program counter
	cpsr  uint32     // current program status register
	__pad uint32
}

			"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" +
			"\xfb\x12\x00\x00\x00\x00\x00\x00\x09\x13\x00\x00\x00\x00\x00\x00" +
			"\x0c\x13\x00\x00\x00\x00\x00\x00\xcb\x13\x00\x00\x00\x00\x00\x00" +
			"\x29\x14\x00\x00\x00\x00\x00\x00\x4e\x14\x00\x00\x00\x00\x00\x00" +
			"\x9d\x14\x00\x00\x00\x00\x00\x00\xd5\x14\x00\x00\x00\x00\x00\x00" +
			"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" +