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Results 1 - 3 of 3 for SRRconst (0.11 sec)
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src/cmd/compile/internal/ssa/_gen/ARM.rules
// using shifted ops this can be done in 4 instructions. (Bswap32 <t> x) && buildcfg.GOARM.Version==5 => (XOR <t> (SRLconst <t> (BICconst <t> (XOR <t> x (SRRconst <t> [16] x)) [0xff0000]) [8]) (SRRconst <t> x [8])) // byte swap for ARMv6 and above (Bswap32 x) && buildcfg.GOARM.Version>=6 => (REV x) // boolean ops -- booleans are represented with 0=false, 1=true (AndB ...) => (AND ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM.go
v_0 := v.Args[0] b := v.Block // match: (Bswap32 <t> x) // cond: buildcfg.GOARM.Version==5 // result: (XOR <t> (SRLconst <t> (BICconst <t> (XOR <t> x (SRRconst <t> [16] x)) [0xff0000]) [8]) (SRRconst <t> x [8])) for { t := v.Type x := v_0 if !(buildcfg.GOARM.Version == 5) { break } v.reset(OpARMXOR) v.Type = t
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 486.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRRconst", auxType: auxInt32, argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)