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Results 1 - 5 of 5 for R6 (0.12 sec)
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src/cmd/asm/internal/asm/testdata/arm64error.s
LDADDALW R5, (R6), RSP // ERROR "illegal combination" LDADDALH R5, (R6), RSP // ERROR "illegal combination" LDADDALB R5, (R6), RSP // ERROR "illegal combination" LDADDD R5, (R6), RSP // ERROR "illegal combination" LDADDW R5, (R6), RSP // ERROR "illegal combination"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 37.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
CLC $8, (R15), n-8(SP) // d507f000f010 XC $256, -8(R15), -8(R15) // b90400afc2a8fffffff8d7ffa000a000 MVCLE 0, R4, R6 // a8640000 MVCLE 4095, R4, R6 // a8640fff MVCLE $4095, R4, R6 // a8640fff MVCLE (R3), R4, R6 // a8643000 MVCLE 10(R3), R4, R6 // a864300a CMP R1, R2 // b9200012 CMP R3, $32767 // a73f7fff
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jul 30 19:29:15 UTC 2025 - 22.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
LDADDLD R5, (R6), ZR // df0065f8 LDADDLW R5, (R6), ZR // df0065b8 LDADDLH R5, (R6), ZR // df006578 LDADDLB R5, (R6), ZR // df006538 LDCLRD R5, (R6), ZR // df1025f8 LDCLRW R5, (R6), ZR // df1025b8 LDCLRH R5, (R6), ZR // df102578
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 95.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
SRLV R4, R5, R6 // a6101900 SRLV $4, R4, R5 // 85104500 SRLV $4, R4 // 84104500 SRLV $32, R4, R5 // 85804500 SRLV $32, R4 // 84804500 MASKEQZ R4, R5, R6 // a6101300 MASKNEZ R4, R5, R6 // a6901300 // CRC32 CRCWBW R4, R5, R6 // a6102400 CRCWHW R4, R5, R6 // a6902400 CRCWWW R4, R5, R6 // a6102500 CRCWVW R4, R5, R6 // a6902500 CRCCWBW R4, R5, R6 // a6102600
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Sep 04 19:24:25 UTC 2025 - 35.5K bytes - Viewed (0) -
lib/fips140/v1.0.0.zip
sure it's zero MOVD $0, R4 // c = 0 MOVD R5, R12 AND $-2, R12 CMPBGE R5, $2, A6 BR E6 A6: MOVD (R8)(R1*1), R6 MULHDU R9, R6 MOVD (R2)(R1*1), R10 ADDC R10, R11 // add to low order bits ADDE R0, R6 ADDC R4, R11 ADDE R0, R6 MOVD R6, R4 MOVD R11, (R2)(R1*1) MOVD (8)(R8)(R1*1), R6 MULHDU R9, R6 MOVD (8)(R2)(R1*1), R10 ADDC R10, R11 // add to low order bits ADDE R0, R6 ADDC R4, R11 ADDE R0, R6 MOVD R6, R4 MOVD R11, (8)(R2)(R1*1) ADD $16, R1 // i*8 + 8 ADD $2, R7 // i++ CMPBLT R7, R12, A6 BR E6 L6: // TODO:...
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jan 29 15:10:35 UTC 2025 - 635K bytes - Viewed (0)