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Results 1 - 9 of 9 for ASUBW (0.05 sec)

  1. src/cmd/internal/obj/loong64/a.out.go

    	AOR
    	AREM
    	AREMU
    
    	ARFE
    
    	ASC
    	ASCV
    
    	ASGT
    	ASGTU
    
    	ASLL
    	ASQRTD
    	ASQRTF
    	ASRA
    	ASRL
    	AROTR
    	ASUB
    	ASUBD
    	ASUBF
    
    	ASUBU
    	ASUBW
    	ADBAR
    	ASYSCALL
    
    	ATEQ
    	ATNE
    
    	AWORD
    
    	AXOR
    
    	AMASKEQZ
    	AMASKNEZ
    
    	// 64-bit
    	AMOVV
    	AMOVVL
    	AMOVVR
    
    	ASLLV
    	ASRAV
    	ASRLV
    	AROTRV
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 5.7K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/riscv/cpu.go

    	// 2.7: Memory Ordering Instructions
    	AFENCE
    	AFENCETSO
    	APAUSE
    
    	// 5.2: Integer Computational Instructions (RV64I)
    	AADDIW
    	ASLLIW
    	ASRLIW
    	ASRAIW
    	AADDW
    	ASLLW
    	ASRLW
    	ASUBW
    	ASRAW
    
    	// 5.3: Load and Store Instructions (RV64I)
    	ALD
    	ASD
    
    	// 7.1: Multiplication Operations
    	AMUL
    	AMULH
    	AMULHU
    	AMULHSU
    	AMULW
    	ADIV
    	ADIVU
    	AREM
    	AREMU
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/riscv/inst.go

    		return &inst{0x13, 0x5, 0x0, 0, 0x0}
    	case ASRLIW:
    		return &inst{0x1b, 0x5, 0x0, 0, 0x0}
    	case ASRLW:
    		return &inst{0x3b, 0x5, 0x0, 0, 0x0}
    	case ASUB:
    		return &inst{0x33, 0x0, 0x0, 1024, 0x20}
    	case ASUBW:
    		return &inst{0x3b, 0x0, 0x0, 1024, 0x20}
    	case ASW:
    		return &inst{0x23, 0x2, 0x0, 0, 0x0}
    	case AWFI:
    		return &inst{0x73, 0x0, 0x5, 261, 0x8}
    	case AXNOR:
    		return &inst{0x33, 0x4, 0x0, 1024, 0x20}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm64/a.out.go

    	ASTLRH
    	ASTLRW
    	ASTLXP
    	ASTLXPW
    	ASTLXR
    	ASTLXRB
    	ASTLXRH
    	ASTLXRW
    	ASTP
    	ASTPW
    	ASTXP
    	ASTXPW
    	ASTXR
    	ASTXRB
    	ASTXRH
    	ASTXRW
    	ASUB
    	ASUBS
    	ASUBSW
    	ASUBW
    	ASVC
    	ASWPAB
    	ASWPAD
    	ASWPAH
    	ASWPALB
    	ASWPALD
    	ASWPALH
    	ASWPALW
    	ASWPAW
    	ASWPB
    	ASWPD
    	ASWPH
    	ASWPLB
    	ASWPLD
    	ASWPLH
    	ASWPLW
    	ASWPW
    	ASXTB
    	ASXTBW
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 18 17:56:30 UTC 2023
    - 18.1K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/riscv/obj.go

    	// Expand binary instructions to ternary ones.
    	if p.Reg == obj.REG_NONE {
    		switch p.As {
    		case AADDI, ASLTI, ASLTIU, AANDI, AORI, AXORI, ASLLI, ASRLI, ASRAI,
    			AADDIW, ASLLIW, ASRLIW, ASRAIW, AADDW, ASUBW, ASLLW, ASRLW, ASRAW,
    			AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA,
    			AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW,
    			AREM, AREMU, AREMW, AREMUW,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/arm64/asm7.go

    func isADDop(op obj.As) bool {
    	switch op {
    	case AADD, AADDS, ASUB, ASUBS, ACMN, ACMP:
    		return true
    	}
    	return false
    }
    
    func isADDWop(op obj.As) bool {
    	switch op {
    	case AADDW, AADDSW, ASUBW, ASUBSW, ACMNW, ACMPW:
    		return true
    	}
    	return false
    }
    
    func isADDSop(op obj.As) bool {
    	switch op {
    	case AADDS, AADDSW, ASUBS, ASUBSW:
    		return true
    	}
    	return false
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/s390x/asmz.go

    			opset(ARISBHG, r)
    			opset(ARISBLG, r)
    			opset(ARISBHGZ, r)
    			opset(ARISBLGZ, r)
    		case ACSG:
    			opset(ACS, r)
    		case ASUB:
    			opset(ASUBC, r)
    			opset(ASUBE, r)
    			opset(ASUBW, r)
    		case ANEG:
    			opset(ANEGW, r)
    		case AFMOVD:
    			opset(AFMOVS, r)
    		case AMOVDBR:
    			opset(AMOVWBR, r)
    		case ACMP:
    			opset(ACMPW, r)
    		case ACMPU:
    			opset(ACMPWU, r)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 17:46:09 UTC 2024
    - 176.7K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/x86/asm6.go

    	{ASUBPD, yxm, Pe, opBytes{0x5c}},
    	{ASUBPS, yxm, Pm, opBytes{0x5c}},
    	{ASUBQ, yaddl, Pw, opBytes{0x83, 05, 0x2d, 0x81, 05, 0x29, 0x2b}},
    	{ASUBSD, yxm, Pf2, opBytes{0x5c}},
    	{ASUBSS, yxm, Pf3, opBytes{0x5c}},
    	{ASUBW, yaddl, Pe, opBytes{0x83, 05, 0x2d, 0x81, 05, 0x29, 0x2b}},
    	{ASWAPGS, ynone, Pm, opBytes{0x01, 0xf8}},
    	{ASYSCALL, ynone, Px, opBytes{0x0f, 0x05}}, // fast syscall
    	{ATESTB, yxorb, Pb, opBytes{0xa8, 0xf6, 00, 0x84, 0x84}},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 146.9K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/opGen.go

    				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
    			},
    		},
    	},
    	{
    		name:   "SUBW",
    		argLen: 2,
    		asm:    riscv.ASUBW,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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