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Results 1 - 6 of 6 for AMULHU (0.23 sec)
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src/cmd/internal/obj/loong64/a.out.go
AMOVDF AMOVDW AMOVF AMOVFD AMOVFW AMOVH AMOVHU AMOVW AMOVWD AMOVWF AMOVWL AMOVWR AMUL AMULD AMULF AMULU AMULH AMULHU AMULW ANEGD ANEGF ANEGW ANEGV ANOOP // hardware nop ANOR AOR AREM AREMU ARFE ASC ASCV ASGT ASGTU ASLL
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 5.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/cpu.go
ASLLIW ASRLIW ASRAIW AADDW ASLLW ASRLW ASUBW ASRAW // 5.3: Load and Store Instructions (RV64I) ALD ASD // 7.1: Multiplication Operations AMUL AMULH AMULHU AMULHSU AMULW ADIV ADIVU AREM AREMU ADIVW ADIVUW AREMW AREMUW // 8.2: Load-Reserved/Store-Conditional Instructions ALRD ASCD ALRW ASCW
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
return &inst{0x73, 0x0, 0x2, 770, 0x18} case AMUL: return &inst{0x33, 0x0, 0x0, 32, 0x1} case AMULH: return &inst{0x33, 0x1, 0x0, 32, 0x1} case AMULHSU: return &inst{0x33, 0x2, 0x0, 32, 0x1} case AMULHU: return &inst{0x33, 0x3, 0x0, 32, 0x1} case AMULW: return &inst{0x3b, 0x0, 0x0, 32, 0x1} case AOR: return &inst{0x33, 0x6, 0x0, 0, 0x0} case AORCB: return &inst{0x13, 0x5, 0x7, 647, 0x14}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/asm.go
opset(ABLTZ, r0) opset(ABGTZ, r0) case AMOVB: opset(AMOVH, r0) case AMOVBU: opset(AMOVHU, r0) case AMUL: opset(AMULU, r0) opset(AMULH, r0) opset(AMULHU, r0) opset(AREM, r0) opset(AREMU, r0) opset(ADIV, r0) opset(ADIVU, r0) case AMULV: opset(AMULVU, r0) opset(AMULHV, r0) opset(AMULHVU, r0) opset(AREMV, r0)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 61.8K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
switch p.As { case AADDI, ASLTI, ASLTIU, AANDI, AORI, AXORI, ASLLI, ASRLI, ASRAI, AADDIW, ASLLIW, ASRLIW, ASRAIW, AADDW, ASUBW, ASLLW, ASRLW, ASRAW, AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA, AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW, AREM, AREMU, AREMW, AREMUW, AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, }, }, { name: "MULHU", argLen: 2, commutative: true, asm: riscv.AMULHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)