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Results 1 - 10 of 108 for 64xf32 (0.1 sec)

  1. tensorflow/compiler/mlir/tensorflow/tests/tpu-merge-variables-with-execute.mlir

          Targs = [tensor<32xf32>, tensor<64xf32>, tensor<8xf32>, tensor<2xf32>],
          Tresults = [tensor<32xf32>, tensor<64xf32>, tensor<8xf32>]}
          : (tensor<32xf32>, tensor<64xf32>, tensor<8xf32>, tensor<2xf32>, tensor<2x!tf_type.string>)
            -> (tensor<32xf32>, tensor<64xf32>, tensor<8xf32>)
        tf_device.return %0#0, %0#1, %0#2 : tensor<32xf32>, tensor<64xf32>, tensor<8xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Oct 31 08:59:10 UTC 2023
    - 24.5K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nhwc.mlir

             data_format = "NCHW",
             epsilon = 1.001000e-05 : f32,
             is_training = false
           } : (tensor<?x64x112x112xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>)
            -> (tensor<?x64x112x112xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<*xf32>)
    
      // CHECK: "tf.FusedBatchNormV3"
      // CHECK-SAME: data_format = "NHWC"
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 7.3K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nchw.mlir

             exponential_avg_factor = 1.0 : f32,
             is_training = true
           }
            : (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>,
               tensor<64xf32>, tensor<64xf32>)
           -> (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>,
               tensor<64xf32>, tensor<64xf32>, tensor<64xf32>)
    
      func.return %y : tensor<1x28x28x64xf32>
    }
    
    // CHECK-LABEL: func @transposeFusedBatchNormGradV3
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir

             exponential_avg_factor = 1.0 : f32,
             is_training = true
           }
            : (tensor<1x64x28x28xf32>, tensor<64xf32>, tensor<64xf32>,
               tensor<64xf32>, tensor<64xf32>)
           -> (tensor<1x64x28x28xf32>, tensor<64xf32>, tensor<64xf32>,
               tensor<64xf32>, tensor<64xf32>, tensor<64xf32>)
    
      func.return %y : tensor<1x64x28x28xf32>
    }
    
    // CHECK-LABEL: bias_add_nchw
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 4.5K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_move_transposes_end.mlir

             exponential_avg_factor = 1.0 : f32,
             is_training = false
           }
            : (tensor<1x112x112x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>)
           -> (tensor<1x112x112x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>)
    
      func.return %2#0 : tensor<1x112x112x64xf32>
    }
    
    // CHECK-LABEL: func @fold_into_pad_with_extra_uses
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9.5K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/lite/tests/quantize-dynamic-range.mlir

      %b = arith.constant dense<-1.23697901> : tensor<64xf32>
      %conv = "tfl.conv_2d"(%arg0, %w, %b) {dilation_h_factor = 1 : i32, dilation_w_factor = 1 : i32, fused_activation_function = "NONE", padding = "SAME", stride_h = 2 : i32, stride_w = 2 : i32} : (tensor<1x224x224x3xf32>, tensor<64x3x3x3xf32>, tensor<64xf32>) -> tensor<1x112x112x64xf32>
      func.return %conv : tensor<1x112x112x64xf32>
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 23 21:09:00 UTC 2024
    - 23.2K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/lite/tests/canonicalize.mlir

      %0 = "tfl.reshape"(%arg0, %shape0) : (tensor<4x4x4xf32>, tensor<2xi32>) -> tensor<16x4xf32>
      %1 = "tfl.reshape"(%0, %shape1) : (tensor<16x4xf32>, tensor<1xi32>) -> tensor<64xf32>
      %2 = "tfl.reshape"(%0, %shape1) : (tensor<16x4xf32>, tensor<1xi32>) -> tensor<64xf32>
      %3 = arith.addf %1, %2 : tensor<64xf32>
      func.return %3 : tensor<64xf32>
    
    // CHECK-LABEL: func @reshape_removeAdjacentWithMultipleUse
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 20.6K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/lite/stablehlo/tests/composite-lowering.mlir

      %9 = mhlo.floor %8 : tensor<64xf32>
      %10 = mhlo.convert %9 : (tensor<64xf32>) -> tensor<64xi32>
      %11 = mhlo.compare  LT, %10, %1,  SIGNED : (tensor<64xi32>, tensor<64xi32>) -> tensor<64xi1>
      %12 = mhlo.add %10, %0 : tensor<64xi32>
      %13 = mhlo.select %11, %12, %10 : tensor<64xi1>, tensor<64xi32>
      %14 = mhlo.reshape %13 : (tensor<64xi32>) -> tensor<64x1xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jun 06 18:45:51 UTC 2024
    - 32.6K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/lite/tests/prepare-quantize-dynamic-range.mlir

            tensor<20xf32>, tensor<20xf32>, tensor<20xf32>,
            tensor<20xf32>, tensor<20xf32>, tensor<20xf32>, tensor<20xf32>,
            tensor<20x20xf32>, none,
            tensor<1x20xf32>, tensor<1x20xf32>,
            none, none, none, none) -> tensor<1x28x20xf32>
        %1 = "quantfork.stats"(%0) {layerStats = dense<[-1.0, 2.0]> : tensor<2xf32>} : (tensor<1x28x20xf32>) -> tensor<1x28x20xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 38.2K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/tensorflow/tests/fused_kernel_matcher.mlir

      // CHECK: %[[VAL_4:.*]] = "tf.Identity"(%[[VAL_3]]) : (tensor<*xf32>) -> tensor<*xf32>
      // CHECK: return %[[VAL_4]]
      %3 = "tf.MatMul"(%arg1, %arg2) {transpose_a = false, transpose_b = false} : (tensor<8x32xf32>, tensor<32x64xf32>) -> tensor<*xf32>
      %4 = "tf.BiasAdd"(%3, %arg0) {data_format = "NHWC"} : (tensor<*xf32>, tensor<64xf32>) -> tensor<*xf32>
      %5 = "tf.Elu"(%4) : (tensor<*xf32>) -> tensor<*xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 13.2K bytes
    - Viewed (0)
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