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src/cmd/asm/internal/asm/testdata/s390x.s
CMP R1, R2 // b9200012 CMP R3, $32767 // a73f7fff CMP R3, $32768 // c23c00008000 CMP R3, $-2147483648 // c23c80000000 CMPU R4, R5 // b9210045 CMPU R6, $4294967295 // c26effffffff CMPW R7, R8 // 1978 CMPW R9, $-32768 // a79e8000 CMPW R9, $-32769 // c29dffff7fff CMPW R9, $-2147483648 // c29d80000000
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Wed Jul 30 19:29:15 GMT 2025 - 22.9K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/loong64enc3.s
MOVWP R5, -32768(R4) // 1efcff13de931000c5038025 MOVWP R5, 32768(R4) // 1e000010de931000c5038025 MOVWP R5, 65536(R4) // 1e040010de931000c5030025 MOVWP R5, 1048576(R4) // 1e400010de931000c5030025 MOVVP R5, -32768(R4) // 1efcff13de931000c5038027 MOVVP R5, 65536(R4) // 1e040010de931000c5030027 MOVVP R5, 1048576(R4) // 1e400010de931000c5030027 MOVWP -32768(R5), R4 // 1efcff13de971000c4038024
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Nov 27 00:46:52 GMT 2025 - 11.2K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
MSR R13, ZCR_EL1 // 0d1218d5 MRS ZCR_EL1, R23 // 171238d5 MSR R17, ZCR_EL1 // 111218d5 SYS $32768, R1 // 018008d5 SYS $32768 // 1f8008d5 MSR $1, DIT // 5f4103d5 // TLBI instruction TLBI VMALLE1IS // 1f8308d5
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Mon Nov 10 17:34:13 GMT 2025 - 96.1K bytes - Click Count (0) -
doc/go_spec.html
uint64 the set of all unsigned 64-bit integers (0 to 18446744073709551615) int8 the set of all signed 8-bit integers (-128 to 127) int16 the set of all signed 16-bit integers (-32768 to 32767) int32 the set of all signed 32-bit integers (-2147483648 to 2147483647) int64 the set of all signed 64-bit integers (-9223372036854775808 to 9223372036854775807)
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Dec 02 23:07:19 GMT 2025 - 286.5K bytes - Click Count (1) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
MOVV R4, FCC0 // 80d81401 // LDPTR.{W/D} and STPTR.{W/D} instructions MOVWP R5, 32764(R4) // 85fc7f25 MOVWP R5, 32(R4) // 85200025 MOVWP R5, 4(R4) // 85040025 MOVWP R5, (R4) // 85000025 MOVVP R5, 32764(R4) // 85fc7f27 MOVVP R5, 32(R4) // 85200027 MOVVP R5, 4(R4) // 85040027 MOVVP R5, (R4) // 85000027 MOVWP 32764(R5), R4 // a4fc7f24 MOVWP 32(R5), R4 // a4200024 MOVWP 4(R5), R4 // a4040024Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Nov 27 00:46:52 GMT 2025 - 44.5K bytes - Click Count (0) -
lib/fips140/v1.0.0-c2097c7c.zip
8 + off)(RSP) #define s2(off) (32*1 + 8 + off)(RSP) #define z1sqr(off) (32*2 + 8 + off)(RSP) #define h(off) (32*3 + 8 + off)(RSP) #define r(off) (32*4 + 8 + off)(RSP) #define hsqr(off) (32*5 + 8 + off)(RSP) #define rsqr(off) (32*6 + 8 + off)(RSP) #define hcub(off) (32*7 + 8 + off)(RSP) #define z2sqr(off) (32*8 + 8 + off)(RSP) #define s1(off) (32*9 + 8 + off)(RSP) #define u1(off) (32*10 + 8 + off)(RSP) #define u2(off) (32*11 + 8 + off)(RSP) // func p256PointAddAffineAs(res, in1 *P256Point, in2 *p256AffinePoint,...
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Sep 25 19:53:19 GMT 2025 - 642.7K bytes - Click Count (0) -
lib/fips140/v1.1.0-rc1.zip
8 + off)(RSP) #define s2(off) (32*1 + 8 + off)(RSP) #define z1sqr(off) (32*2 + 8 + off)(RSP) #define h(off) (32*3 + 8 + off)(RSP) #define r(off) (32*4 + 8 + off)(RSP) #define hsqr(off) (32*5 + 8 + off)(RSP) #define rsqr(off) (32*6 + 8 + off)(RSP) #define hcub(off) (32*7 + 8 + off)(RSP) #define z2sqr(off) (32*8 + 8 + off)(RSP) #define s1(off) (32*9 + 8 + off)(RSP) #define u1(off) (32*10 + 8 + off)(RSP) #define u2(off) (32*11 + 8 + off)(RSP) // func p256PointAddAffineAs(res, in1 *P256Point, in2 *p256AffinePoint,...
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Dec 11 16:27:41 GMT 2025 - 663K bytes - Click Count (0)