- Sort Score
- Result 10 results
- Languages All
Results 1 - 2 of 2 for DIVW (0.01 sec)
-
src/cmd/asm/internal/asm/testdata/ppc64.s
MULLDV R3, R4, R5 // 7ca41dd2 MULLDVCC R3, R4, R5 // 7ca41dd3 DIVD R3,R4 // 7c841bd2 DIVD R3, R4, R5 // 7ca41bd2 DIVW R3, R4 // 7c841bd6 DIVW R3, R4, R5 // 7ca41bd6 DIVDCC R3,R4, R5 // 7ca41bd3 DIVWCC R3,R4, R5 // 7ca41bd7 DIVDU R3, R4, R5 // 7ca41b92
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Oct 29 13:14:38 UTC 2024 - 51K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
MULW X5, X6, X7 // bb035302 // 13.2: Division Operations DIV X5, X6, X7 // b3435302 DIVU X5, X6, X7 // b3535302 REM X5, X6, X7 // b3635302 REMU X5, X6, X7 // b3735302 DIVW X5, X6, X7 // bb435302 DIVUW X5, X6, X7 // bb535302 REMW X5, X6, X7 // bb635302 REMUW X5, X6, X7 // bb735302 // 14.2: Load-Reserved/Store-Conditional (Zalrsc) LRW (X5), X6 // 2fa30214
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Oct 25 12:05:29 UTC 2024 - 16.8K bytes - Viewed (0)