// all spatial dimensions.
    const int64_t filter_channels = GetDimSize(filter_ty, num_spatial_dims);
    // TensorFlow convolution op verifies that the number of input channels is
    // divisible by the number of filter channels.
    // For depthwise convolution the feature_group_count argument would be set
    // to the input feature dimension.
    const int64_t feature_group_count =

}

def TF_ConvOp : TF_Op<"Conv", [Pure]> {
  let summary = [{
Computes a N-D convolution given (N+1+batch_dims)-D `input` and (N+2)-D `filter` tensors.
  }];

  let description = [{
General function for computing a N-D convolution. It is required that
`1 <= N <= 3`.
  }];

  let arguments = (ins

    Intel developed a number of optimized deep learning primitives: In addition
    to matrix multiplication and convolution, these building blocks include:
    Direct batched convolution Pooling: maximum, minimum, average Normalization:
    LRN, batch normalization Activation: rectified linear unit (ReLU) Data

  let summary = "Applies automatic space to depth transform for the first or frontier convolutions consume host inputs on TPU.";

  let description = [{
    Automatic space to depth transform is done by adding space to depth transform op after host input
    and applying space to depth transform for the first convolution and its backprop filter on TPU.

    For example, original program:

    ```mlir

      dnums.kernel_spatial_dimensions_size()) {
    return op.emitOpError() << "Both arguments to convolution must have "
                            << "same number of dimensions.\n";
  }

  if (dnums.input_spatial_dimensions_size() !=
      dnums.output_spatial_dimensions_size()) {
    return op.emitOpError() << "Both input and output of convolution must have "
                            << "same number of dimensions.\n";
  }

            quantized_graph->tensors()->Get(op->inputs()->Get(1));
        EXPECT_EQ(weights_tensor->type(), TensorType_INT8);
      }
    }
  }
  // Ensure that there were exactly two convolutions in the model.
  EXPECT_EQ(num_conv_ops, 2);
}

TEST_F(QuantizeWeightsTest, SharedWeights_Dequantize) {
  LoadSharedWeightsModel();
  flatbuffers::FlatBufferBuilder builder;

// between hosts.
std::unique_ptr<OperationPass<mlir::ModuleOp>>
CreateTPUCompileOpReplicationPass();

// Creates a pass that applies space to depth transform
// for the first or frontier convolutions consume host inputs on TPU.
std::unique_ptr<OperationPass<ModuleOp>> CreateTPUSpaceToDepthPass();

// Adjusts the device on TPUCopyWithDynamicShape ops.
std::unique_ptr<OperationPass<ModuleOp>>