prog.From = a[0]
				prog.Reg = p.getRegister(prog, op, &a[1])
				break
			}
		} else if p.arch.Family == sys.Loong64 {
			if arch.IsLoong64RDTIME(op) {
				// The Loong64 RDTIME family of instructions is a bit special,
				// in that both its register operands are outputs
				prog.To = a[0]
				if a[1].Type != obj.TYPE_REG {

	CSRRW	X10, CYCLE, X5				// f31205c0
	CSRRW	$2, TIME, X5				// f35211c0
	CSRRWI	$2, TIME, X5				// f35211c0

	// 8.1: Base Counters and Timers (Zicntr)
	RDCYCLE		X5				// f32200c0
	RDTIME		X5				// f32210c0
	RDINSTRET	X5				// f32220c0

	// 10.1: Zihintpause Extension for Pause Hint
	PAUSE						// 0f000001

	// 12.3: Integer Conditional Operations (Zicond)
	CZEROEQZ	X5, X6, X7			// b353530e