SLLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	SRLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	SRAI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	RORI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	SLLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	SRLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"

	{"0/0", "division by zero"},
	{"3/0", "division by zero"},
	{"(1<<63)/0", "divide of value with high bit set"},
	{"3%0", "modulo by zero"},
	{"(1<<63)%0", "modulo of value with high bit set"},
	{"3<<-4", "negative left shift count"},
	{"3<<(1<<63)", "negative left shift count"},
	{"3>>-4", "negative right shift count"},
	{"3>>(1<<63)", "negative right shift count"},
	{"(1<<63)>>2", "right shift of value with high bit set"},
	{"(1<<62)>>2", ""},

	switch name {
	case "CR":
		if 0 <= n && n <= 7 {
			return ppc64.REG_CR0 + n, true
		}
	case "A":
		if 0 <= n && n <= 8 {
			return ppc64.REG_A0 + n, true
		}
	case "VS":
		if 0 <= n && n <= 63 {
			return ppc64.REG_VS0 + n, true
		}
	case "V":
		if 0 <= n && n <= 31 {
			return ppc64.REG_V0 + n, true
		}
	case "F":
		if 0 <= n && n <= 31 {
			return ppc64.REG_F0 + n, true
		}
	case "R":

var amd64OperandTests = []operandTest{
	{"$(-1.0)", "$(-1.0)"},
	{"$(0.0)", "$(0.0)"},
	{"$(0x2000000+116)", "$33554548"},
	{"$(0x3F<<7)", "$8064"},
	{"$(112+8)", "$120"},
	{"$(1<<63)", "$-9223372036854775808"},
	{"$-1", "$-1"},
	{"$0", "$0"},
	{"$0-0", "$0"},
	{"$0-16", "$-16"},
	{"$0x000FFFFFFFFFFFFF", "$4503599627370495"},
	{"$0x01", "$1"},
	{"$0x02", "$2"},
	{"$0x04", "$4"},

0000100 43 58 12 b2 5a a5 c6 7d 68 55 88 d4 98 75 18 6d
0000110 08 d1 1f 8f 5a 9e 96 ee 45 cf a4 84 4e 4b e8 50
0000120 a7 13 d9 06 de 52 81 97 36 b2 d7 b8 fc 2b 5f 55
0000130 23 1f 32 59 cf 30 27 fb e2 8a b9 de 45 dd 63 9c
0000140 4b b5 8b 96 4c 7a 62 62 cc a1 a7 cf fa f1 fe dd
0000150 54 62 11 bf 36 78 b3 c7 b1 b5 f2 61 4d 4e dd 66
0000160 32 2e e6 70 34 5f f4 c9 e6 6c 43 6f da 6b c6 c3
0000170 09 2c ce 09 57 7f d2 7e b4 23 ba 7c 1b 99 bc 22

//	}
	SLL	$19, R21	// 0015acc0
	SLLV	$19, R21	// 0015acf8
	SRL	$31, R17	// 00118fc2
	SRLV	$31, R17	// 00118ffa
	SRA	$3, R12		// 000c60c3
	SRAV	$12, R3		// 00031b3b
	ROTR	$12, R8		// 00284302
	ROTRV	$63, R22	// 0036b7fe


//	LAND/LXOR/LNOR/LOR rreg ',' rreg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	AND	R14, R8		// 010e4024
	XOR	R15, R9		// 012f4826
	NOR	R16, R10	// 01505027

	AND	R1@>33, R2
	AND	$(1<<63), R1                        // AND	$-9223372036854775808, R1       // 21004192
	AND	$(1<<63-1), R1                      // AND	$9223372036854775807, R1        // 21f84092
	ORR	$(1<<63), R1                        // ORR	$-9223372036854775808, R1       // 210041b2
	ORR	$(1<<63-1), R1                      // ORR	$9223372036854775807, R1        // 21f840b2

			if i == 0 {
				c &= 0x7f // Ignore signal bit in first byte
			}
			if (x >> 56) > 0 {
				p.err = ErrHeader // Integer overflow
				return 0
			}
			x = x<<8 | uint64(c)
		}
		if (x >> 63) > 0 {
			p.err = ErrHeader // Integer overflow
			return 0
		}
		if inv == 0xff {
			return ^int64(x)
		}
		return int64(x)
	}

	// Normal case is base-8 (octal) format.

	BCLR	X23, X24, X25				// b31c7c49
	BCLR	$63, X24				// 131cfc4b
	BCLRI	$1, X25, X26				// 139d1c48
	BEXT	X26, X28, X29				// b35eae49
	BEXT	$63, X28				// 135efe4b
	BEXTI	$1, X29, X30				// 13df1e48
	BINV	X30, X5, X6				// 3393e269
	BINV	$63, X6					// 1313f36b
	BINVI	$1, X7, X8				// 13941368
	BSET	X8, X9, X10				// 33958428
	BSET	$63, X9					// 9394f42b
	BSETI	$1, X10, X11				// 93151528

// and they are consistent with disassembler decoding.
// TODO means they cannot be handled by current assembler.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$-8

	AND $(1<<63), R1                           // AND $-9223372036854775808, R1     // 21004192
	ADCW ZR, R8, R10                           // 0a011f1a
	ADC R0, R2, R12                            // 4c00009a