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src/archive/zip/register.go
panic("decompressor already registered") } } // RegisterCompressor registers custom compressors for a specified method ID. // The common methods [Store] and [Deflate] are built in. func RegisterCompressor(method uint16, comp Compressor) { if _, dup := compressors.LoadOrStore(method, comp); dup { panic("compressor already registered") } } func compressor(method uint16) Compressor {
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Oct 13 18:36:46 GMT 2023 - 3.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/operand_test.go
var amd64BadOperandTests = []badOperandTest{ {"[", "register list: expected ']', found EOF"}, {"[4", "register list: bad low register in `[4`"}, {"[]", "register list: bad low register in `[]`"}, {"[f-x]", "register list: bad low register in `[f`"}, {"[r10-r13]", "register list: bad low register in `[r10`"}, {"[k3-k6]", "register list: bad low register in `[k3`"}, {"[X0]", "register list: expected '-' after `[X0`, found ']'"},
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 29 18:31:05 GMT 2023 - 23.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VEXTRACTPS $-1, X1, AX // c4e37917c8ff VPEXTRB $-1, X1, AX // c4e37914c8ff VPEXTRD $-1, X1, AX // c4e37916c8ff VPEXTRQ $-1, X1, AX // c4e3f916c8ff // EVEX: High-16 X registers. VADDPD X30, X1, X0 // 6291f50858c6 VADDPD X2, X29, X0 // 62f1950058c2 VADDPD X30, X29, X0 // 6291950058c6 VADDPD X2, X1, X28 // 6261f50858e2
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0) -
misc/wasm/wasm_exec.js
this._nextCallbackTimeoutID++; this._scheduledTimeouts.set(id, setTimeout( () => { this._resume(); while (this._scheduledTimeouts.has(id)) { // for some reason Go failed to register the timeout event, log and try again // (temporary workaround for https://github.com/golang/go/issues/28975) console.warn("scheduleTimeoutEvent: missed timeout event"); this._resume(); }
JavaScript - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Mon May 22 17:47:47 GMT 2023 - 16.3K bytes - Viewed (1) -
src/cmd/asm/internal/arch/arch.go
// General registers with ABI names. register["ZERO"] = riscv.REG_ZERO register["RA"] = riscv.REG_RA register["SP"] = riscv.REG_SP register["GP"] = riscv.REG_GP register["TP"] = riscv.REG_TP register["T0"] = riscv.REG_T0 register["T1"] = riscv.REG_T1 register["T2"] = riscv.REG_T2 register["S0"] = riscv.REG_S0 register["S1"] = riscv.REG_S1 register["A0"] = riscv.REG_A0 register["A1"] = riscv.REG_A1
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Mar 21 06:51:28 GMT 2023 - 21.3K bytes - Viewed (0) -
doc/asm.html
Some symbols, such as <code>R1</code> or <code>LR</code>, are predefined and refer to registers. The exact set depends on the architecture. </p> <p> There are four predeclared symbols that refer to pseudo-registers. These are not real registers, but rather virtual registers maintained by the toolchain, such as a frame pointer. The set of pseudo-registers is the same for all architectures: </p> <ul> <li>
HTML - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Tue Nov 28 19:15:27 GMT 2023 - 36.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
MOV $0, 0(SP) // ERROR "constant load must target register" MOV $0, 8(SP) // ERROR "constant load must target register" MOV $1234, 0(SP) // ERROR "constant load must target register" MOV $1234, 8(SP) // ERROR "constant load must target register" MOVB $1, X5 // ERROR "unsupported constant load" MOVH $1, X5 // ERROR "unsupported constant load" MOVW $1, X5 // ERROR "unsupported constant load"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Sun Apr 07 03:32:27 GMT 2024 - 2.8K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm.go
(op1 << 20) | // MCR/MRC ((int64(bits) ^ arm.C_SCOND_XOR) << 28) | // scond ((x0 & 15) << 8) | //coprocessor number ((x1 & 7) << 21) | // coprocessor operation ((x2 & 15) << 12) | // ARM register ((x3 & 15) << 16) | // Crn ((x4 & 15) << 0) | // Crm ((x5 & 7) << 5) | // coprocessor information (1 << 4) /* must be set */ return offset, arm.AMRC, true }
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Nov 18 17:59:44 GMT 2022 - 6.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
FMOVS 0x44332211(R1), F2 // FMOVS 1144201745(R1), F2 FMOVD 0x1000000(R1), F2 // FMOVD 16777216(R1), F2 FMOVD 0x44332211(R1), F2 // FMOVD 1144201745(R1), F2 // shifted or extended register offset. MOVD (R2)(R6.SXTW), R4 // 44c866f8 MOVD (R3)(R6), R5 // 656866f8 MOVD (R3)(R6*1), R5 // 656866f8 MOVD (R2)(R6), R4 // 446866f8
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// ($1 << 20) | /* MCR/MRC */ // (($2^C_SCOND_XOR) << 28) | /* scond */ // (($3 & 15) << 8) | /* coprocessor number */ // (($5 & 7) << 21) | /* coprocessor operation */ // (($7 & 15) << 12) | /* arm register */ // (($9 & 15) << 16) | /* Crn */ // (($11 & 15) << 0) | /* Crm */ // (($12 & 7) << 5) | /* coprocessor information */ // (1<<4)); /* must be set */ // outcode(AMRC, Always, &nullgen, 0, &g); // }
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0)