VADDPD 15(CX)(AX*1), Y10, Y29   // 6261ad2858ac010f000000
	VADDPD 15(CX)(AX*1), Y28, Y10   // 62719d205894010f000000
	VADDPD 15(CX)(AX*2), Y0, Y29    // 6261fd2858ac410f000000
	VADDPD 15(CX)(AX*2), Y28, Y1    // 62f19d20588c410f000000
	VADDPD 15(CX)(AX*2), Y28, Y29   // 62619d2058ac410f000000
	VADDPD 15(CX)(AX*2), Y10, Y29   // 6261ad2858ac410f000000
	VADDPD 15(CX)(AX*2), Y28, Y10   // 62719d205894410f000000

	RLDCRCC $0, R4, $-16, R6        // 788606f3
	RLDICL $0, R4, $15, R6          // 788603c0
	RLDICLCC $0, R4, $15, R6        // 788603c1
	RLDICR $0, R4, $15, R6          // 788603c4
	RLDICRCC $0, R4, $15, R6        // 788603c5
	RLDIC $0, R4, $15, R6           // 788603c8
	RLDICCC $0, R4, $15, R6         // 788603c9
	CLRLSLWI $16, R5, $8, R4        // 54a4422e
	CLRLSLDI $24, R4, $2, R3        // 78831588
	RLDCR	$1, R1, $-16, R1        // 78210ee4

	VLEF	$2, (R0), V31           // e7f000002803
	VLEH	$3, (R12), V16          // e700c0003801
	VLEB	$15, 4095(R9), V15      // e7f09ffff000
	VSTEG	$1, V30, (R1)(R2*1)     // e7e21000180a
	VSTEF	$3, V2, (R9)            // e7209000300b
	VSTEH	$7, V31, (R2)           // e7f020007809
	VSTEB	$15, V29, 4094(R12)     // e7d0cffef808
	VMSLG	V21, V22, V23, V24      // e78563007fb8
	VMSLEG  V21, V22, V23, V24      // e78563807fb8

	VCMEQ V24.S4, V13.S4, V12.S4                                // ac8db86e
	VCNT V13.B8, V11.B8                                         // ab59200e
	VMOV V31.B[15], V18                                         // f2071f5e
	VDUP V31.B[15], V18                                         // f2071f5e
	VDUP V31.B[13], V20.B16                                     // f4071b4e

//			(0xe << 24) |		/* opcode */
//			($1 << 20) |		/* MCR/MRC */
//			(($2^C_SCOND_XOR) << 28) |		/* scond */
//			(($3 & 15) << 8) |	/* coprocessor number */
//			(($5 & 7) << 21) |	/* coprocessor operation */
//			(($7 & 15) << 12) |	/* arm register */
//			(($9 & 15) << 16) |	/* Crn */
//			(($11 & 15) << 0) |	/* Crm */
//			(($12 & 7) << 5) |	/* coprocessor information */
//			(1<<4));			/* must be set */

	VSRI	$8, V1.H8, V2.H8                // 2244186f
	VSRI	$2, V1.B8, V2.B8                // 22440e2f
	VSRI	$2, V1.B16, V2.B16              // 22440e6f
	VSLI	$7, V2.B16, V3.B16              // 43540f6f
	VSLI	$15, V3.H4, V4.H4               // 64541f2f
	VSLI	$31, V5.S4, V6.S4               // a6543f6f
	VSLI	$63, V7.D2, V8.D2               // e8547f6f
	VUSRA	$8, V2.B16, V3.B16              // 4314086f

	VDUP	V8.B[16], V3.B16                                 // ERROR "register element index out of range 0 to 15"
	VDUP	V8.B[17], V3.B8                                  // ERROR "register element index out of range 0 to 15"
	VDUP	V8.H[9], V3.H4                                   // ERROR "register element index out of range 0 to 7"