MOVB	$255, 4096(R4)        // ebff40000152
	MOVB	$-128, -524288(R5)    // eb8050008052
	MOVB	$1, -524289(R6)       // c0a1fff7ffff41aa60009201a000

	// RX (12-bit displacement) and RXY (20-bit displacement) instruction encoding (e.g: ST vs STY)
	MOVW	R1, 4095(R2)(R3)       // 50132fff
	MOVW	R1, 4096(R2)(R3)       // e31320000150
	MOVWZ	R1, 4095(R2)(R3)       // 50132fff
	MOVWZ	R1, 4096(R2)(R3)       // e31320000150

	// Hex constant 0x20004000000
	MOVD $2199090364416, R5         // 60058001
	// Hex constant 0xFFFFFE0004000000
	MOVD $-2198956146688, R5        // 38a08001
	// TODO: On GOPPC64={power8,power9}, this is preprocessed into MOVD $-1, R5; RLDC R5, $33, $63, R5.
	//       This only captures the MOVD. Should the RLDC be appended to the encoding by the test?
	// Hex constant 0xFFFFFFFE00000001

	VADDPS.BCST 2032(DX), Z28, Z29       // 62611c5058aaf0070000
	VADDPS.BCST 2032(DX)(AX*2), Z0, Z29  // 62617c5858ac42f0070000
	VADDPS.BCST 2032(DX)(AX*2), Z1, Z29  // 6261745858ac42f0070000
	// Forced EVEX encoding due to suffixes.
	VADDPD.BCST 2032(DX), X0, X0 // 62f1fd185882f0070000
	VADDPD.BCST 2032(DX), Y0, Y0 // 62f1fd385882f0070000
	// Test new Z-cases one-by-one.
	//
	// Zevex_i_r_k_rm.

	AND	$1, ZR                              // fb0340b2ff031b8a
	ANDW	$1, ZR                              // fb030032ff031b0a
	// TODO: this could have better encoding
	ANDW	$-1, R10                            // 1b0080124a011b0a
	AND	$8, R0, RSP                         // 1f007d92
	ORR	$8, R0, RSP                         // 1f007db2
	EOR	$8, R0, RSP                         // 1f007dd2

// license that can be found in the LICENSE file.

// The cases are auto-generated by disassembler.
// The uncommented cases means they can be handled by assembler
// and they are consistent with disassembler decoding.
// TODO means they cannot be handled by current assembler.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$-8