typs[101] = newSig(params(typs[100], typs[3]), nil)
	typs[102] = newSig(params(typs[100], typs[3]), params(typs[6]))
	typs[103] = types.NewChan(typs[2], types.Csend)
	typs[104] = newSig(params(typs[103], typs[3]), nil)
	typs[105] = newSig(params(typs[103]), nil)
	typs[106] = newSig(params(typs[2]), params(typs[15]))
	typs[107] = types.NewArray(typs[0], 3)

	_ = x[SPOP_RVALE3-95]
	_ = x[SPOP_IVAC-96]
	_ = x[SPOP_ISW-97]
	_ = x[SPOP_CSW-98]
	_ = x[SPOP_CISW-99]
	_ = x[SPOP_ZVA-100]
	_ = x[SPOP_CVAC-101]
	_ = x[SPOP_CVAU-102]
	_ = x[SPOP_CIVAC-103]
	_ = x[SPOP_IGVAC-104]
	_ = x[SPOP_IGSW-105]
	_ = x[SPOP_IGDVAC-106]
	_ = x[SPOP_IGDSW-107]
	_ = x[SPOP_CGSW-108]
	_ = x[SPOP_CGDSW-109]
	_ = x[SPOP_CIGSW-110]
	_ = x[SPOP_CIGDSW-111]

	case arg_Xns_mem_post_size__1_0__2_1__4_2__8_3:
		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
		size := (x >> 10) & 3
		return MemImmediate{Rn, AddrPostIndex, int32(1 << size)}

	case arg_Xns_mem_post_size__2_0__4_1__8_2__16_3:
		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
		size := (x >> 10) & 3
		return MemImmediate{Rn, AddrPostIndex, int32(2 << size)}

	case arg_Xns_mem_post_size__3_0__6_1__12_2__24_3:

	case 0x7:
		regCnt = 1
	case 0xa:
		regCnt = 2
	case 0x6:
		regCnt = 3
	case 0x2:
		regCnt = 4
	default:
		regCnt = -1
	}
	// Q:size
	arng := ((list>>30)&1)<<2 | (list>>10)&3
	switch arng {
	case 0:
		t = "B8"
	case 4:
		t = "B16"
	case 1:
		t = "H4"
	case 5:
		t = "H8"
	case 2:
		t = "S2"
	case 6:
		t = "S4"
	case 3:
		t = "D1"
	case 7:

	PT_VR26                 = 100 // Vector register 26
	PT_VR27                 = 101 // Vector register 27
	PT_VR28                 = 102 // Vector register 28
	PT_VR29                 = 103 // Vector register 29
	PT_VR30                 = 104 // Vector register 30
	PT_VR31                 = 105 // Vector register 31
	PT_PSWG                 = 106 // PSWG
	PT_PSWG0                = 106 // Bytes 0-3

	C_EXT     = 2   // External symbol
	C_STAT    = 3   // Static symbol
	C_BLOCK   = 100 // Beginning or end of inner block
	C_FCN     = 101 // Beginning or end of function
	C_FILE    = 103 // Source file name and compiler information
	C_HIDEXT  = 107 // Unnamed external symbol
	C_BINCL   = 108 // Beginning of include file
	C_EINCL   = 109 // End of include file
	C_WEAKEXT = 111 // Weak external symbol

			if t&7 != 0 {
				ldr.Errorf(s, "invalid address: %x for relocation type: R_AARCH64_LD64_GOT_LO12_NC", t)
			}
			var o1 uint32
			o1 |= uint32(t&0xfff) << (10 - 3)
			return val | int64(uint64(o1)), noExtReloc, isOk
		} else {
			ldr.Errorf(s, "unsupported instruction for %x R_GOTARM64", val)
		}

	case objabi.R_ARM64_PCREL:
		if (val>>24)&0x9f == 0x90 {

	// VRV scatter
	{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
	{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},

	// VRV gather
	{i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
	{i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},

	// VRS element shift/rotate and load gr to/from vr element
	{i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},

		o1 = c.omvl(p, &p.From, int(p.To.Reg))

	case 102: /* movw tlsvar,R, initial exec*/
		o1 = c.omvl(p, &p.From, int(p.To.Reg))
		o2 = c.olrr(int(p.To.Reg)&15, (REGPC & 15), int(p.To.Reg), int(p.Scond))

	case 103: /* word tlsvar, local exec */
		if p.To.Sym == nil {
			c.ctxt.Diag("nil sym in tls %v", p)
		}
		if p.To.Offset != 0 {
			c.ctxt.Diag("offset against tls var in %v", p)
		}

	IMAGE_SYM_CLASS_FAR_EXTERNAL     = 68 /* Not in PECOFF v8 spec */
	IMAGE_SYM_CLASS_BLOCK            = 100
	IMAGE_SYM_CLASS_FUNCTION         = 101
	IMAGE_SYM_CLASS_END_OF_STRUCT    = 102
	IMAGE_SYM_CLASS_FILE             = 103
	IMAGE_SYM_CLASS_SECTION          = 104
	IMAGE_SYM_CLASS_WEAK_EXTERNAL    = 105
	IMAGE_SYM_CLASS_CLR_TOKEN        = 107
	IMAGE_REL_I386_ABSOLUTE          = 0x0000
	IMAGE_REL_I386_DIR16             = 0x0001