FLDLG2                                  // d9ec
	FLDPI                                   // d9eb
	//TODO: FMUL F2, F0                     // d8ca
	//TODO: FMUL F3, F0                     // d8cb
	//TODO: FMUL F0, F2                     // dcca
	//TODO: FMUL F0, F3                     // dccb
	//TODO: FMULS (BX)                      // d80b
	//TODO: FMULS (R11)                     // 41d80b

	v_0 := v.Args[0]
	b := v.Block
	// match: (MUL (NEG x) y)
	// result: (MNEG x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != OpARM64NEG {
				continue
			}
			x := v_0.Args[0]
			y := v_1
			v.reset(OpARM64MNEG)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (MUL x (MOVDconst [-1]))
	// result: (NEG x)
	for {