boundaries.

*   XLA compilation:

    *   `tf.function(experimental_compile=True)` has become a stable API,
        renamed `tf.function(jit_compile=True)`.
    *   XLA can now compile MirroredStrategy: the step function passed
        to`strategy.run` can now be annoted with `jit_compile=True`.

*   `tf.distribute`:

    *   Rename `experimental_prefetch_to_device` in `tf.distribute.InputOptions`

X1, YDIG, T1, ADD2H VMALF X0, YDIG, T0, ADD1 // T0 Free->ADD1 VMALF X1, YDIG, T1, ADD2 // T1 Free->ADD2 VREPF $0, Y0, YDIG VMALF X0, YDIG, ADD1H, ADD3 VMALF X1, YDIG, ADD2H, ADD4 VMALHF X0, YDIG, ADD1H, ADD3H // ADD1H Free->ADD3H VMALHF X1, YDIG, ADD2H, ADD4H // ADD2H Free->ADD4H , YDIG Free->ZER VZERO ZER VL 32(CPOOL), SEL1 VPERM ZER, ADD1, SEL1, RED3 // [d0 0 0 d0] VSLDB $12, ADD2, ADD1, T0 // ADD1 Free->T0 VSLDB $12, T2, ADD2, T1 // ADD2 Free->T1, T2 Free VACCQ T0, RED1, CAR1 VAQ T0, RED1, T0...

X1, YDIG, T1, ADD2H VMALF X0, YDIG, T0, ADD1 // T0 Free->ADD1 VMALF X1, YDIG, T1, ADD2 // T1 Free->ADD2 VREPF $0, Y0, YDIG VMALF X0, YDIG, ADD1H, ADD3 VMALF X1, YDIG, ADD2H, ADD4 VMALHF X0, YDIG, ADD1H, ADD3H // ADD1H Free->ADD3H VMALHF X1, YDIG, ADD2H, ADD4H // ADD2H Free->ADD4H , YDIG Free->ZER VZERO ZER VL 32(CPOOL), SEL1 VPERM ZER, ADD1, SEL1, RED3 // [d0 0 0 d0] VSLDB $12, ADD2, ADD1, T0 // ADD1 Free->T0 VSLDB $12, T2, ADD2, T1 // ADD2 Free->T1, T2 Free VACCQ T0, RED1, CAR1 VAQ T0, RED1, T0...

## 0.124.1

### Fixes

* 🐛 Fix handling arbitrary types when using `arbitrary_types_allowed=True`. PR [#14482](https://github.com/fastapi/fastapi/pull/14482) by [@tiangolo](https://github.com/tiangolo).

### Docs