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RELEASE.md
AVX512_BF16, AMX, etc. ([Intel Cascade Lake](https://www.intel.com/content/www/us/en/products/platforms/details/cascade-lake.html) and newer CPUs.) * [Example performance speedups.](https://medium.com/intel-analytics-software/leverage-intel-deep-learning-optimizations-in-tensorflow-129faa80ee07)Created: Tue Apr 07 12:39:13 GMT 2026 - Last Modified: Mon Mar 30 18:31:38 GMT 2026 - 746.5K bytes - Click Count (3) -
docs/en/docs/release-notes.md
Created: Sun Apr 05 07:19:11 GMT 2026 - Last Modified: Fri Apr 03 12:07:04 GMT 2026 - 631K bytes - Click Count (0) -
lib/fips140/v1.26.0.zip
" ) // This file contains two implementations of AES-GCM. The first implementation // (useGHASH) uses the KMCTR instruction to encrypt using AES in counter mode // and the KIMD instruction for GHASH. The second implementation (useGCM) uses // the newer KMA instruction which performs both operations (but still requires // KIMD to hash large nonces). // Keep in sync with crypto/tls.hasAESGCMHardwareSup. var useGHASH = cpu.S390XHasAES && cpu.S390XHasAESCTR && cpu.S390XHasGHASH var useGCM = useGHASH...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Jan 08 17:58:32 GMT 2026 - 660.3K bytes - Click Count (0) -
lib/fips140/v1.0.0-c2097c7c.zip
" ) // This file contains two implementations of AES-GCM. The first implementation // (useGHASH) uses the KMCTR instruction to encrypt using AES in counter mode // and the KIMD instruction for GHASH. The second implementation (useGCM) uses // the newer KMA instruction which performs both operations (but still requires // KIMD to hash large nonces). // Keep in sync with crypto/tls.hasAESGCMHardwareSup. var useGHASH = cpu.S390XHasAES && cpu.S390XHasAESCTR && cpu.S390XHasGHASH var useGCM = useGHASH...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Sep 25 19:53:19 GMT 2025 - 642.7K bytes - Click Count (0)