$headings-line-height;\n  color: var(--#{$prefix}heading-color);\n}\n\nh1 {\n  @extend %heading;\n  @include font-size($h1-font-size);\n}\n\nh2 {\n  @extend %heading;\n  @include font-size($h2-font-size);\n}\n\nh3 {\n  @extend %heading;\n  @include font-size($h3-font-size);\n}\n\nh4 {\n  @extend %heading;\n  @include font-size($h4-font-size);\n}\n\nh5 {\n  @extend %heading;\n  @include font-size($h5-font-size);\n}\n\nh6 {\n  @extend %heading;\n  @include font-size($h6-font-size);\n}\n\n\n// Reset margins...

    *   Add name argument to `tf.string_split` and `tf.strings_split`.
    *   Extend `tf.strings.split` to support inputs with any rank.
    *   Added `tf.random.binomial`.
    *   Added `key` and `skip` methods to `random.experimental.Generator`.
    *   Extend `tf.function` with basic support for CompositeTensors arguments
        (such as `SparseTensor` and `RaggedTensor`).

### Avoiding permanent beta

From Kubernetes 1.20 onwards, SIG Architecture will implement a new policy to transition all REST APIs out of beta within nine months. The idea behind the new policy is to avoid features staying in beta for a long time. Once a new API enters beta, it will have nine months to either:

* [Forbid Extra Query Parameters](https://fastapi.tiangolo.com/tutorial/query-param-models/#forbid-extra-query-parameters)
* [Forbid Extra Headers](https://fastapi.tiangolo.com/tutorial/header-param-models/#forbid-extra-headers)
* [Forbid Extra Cookies](https://fastapi.tiangolo.com/tutorial/cookie-param-models/#forbid-extra-cookies)

### Features

	DPPS $7, X2, X11                        // 66440f3a40da07
	DPPS $7, X11, X11                       // 66450f3a40db07
	EMMS                                    // 0f77
	//TODO: ENTERQ $0x12, $0xf123           // c823f112
	EXTRACTPS $0, X2, (BX)                  // 660f3a171300
	EXTRACTPS $1, X11, (BX)                 // 66440f3a171b01
	EXTRACTPS $2, X2, (R11)                 // 66410f3a171302

// Divide by 2 ADDS $-1, y0, t0 ADCS const0, y1, t1 ADCS $0, y2, t2 ADCS const1, y3, t3 ADC $0, ZR, hlp0 ANDS $1, y0, ZR CSEL EQ, y0, t0, t0 CSEL EQ, y1, t1, t1 CSEL EQ, y2, t2, t2 CSEL EQ, y3, t3, t3 AND y0, hlp0, hlp0 EXTR $1, t0, t1, y0 EXTR $1, t1, t2, y1 EXTR $1, t2, t3, y2 EXTR $1, t3, hlp0, y3 STy(y3out) LDx(x1in) LDy(s) CALL p256MulInternal<>(SB) STy(s) p256MulBy2Inline STx(tmp) LDx(m) CALL p256SqrInternal<>(SB) LDx(tmp) CALL p256SubInternal<>(SB) STx(x3out) LDy(s) CALL p256SubInternal<>(SB)...