MOVD sign+24(FP), hlp0 MOVD sel+32(FP), hlp1 MOVD zero+40(FP), t2 MOVD $1, t0 CMP $0, t2 CSEL EQ, ZR, t0, t2 CMP $0, hlp1 CSEL EQ, ZR, t0, hlp1 MOVD p256const0<>(SB), const0 MOVD p256const1<>(SB), const1 EOR t2<<1, hlp1 // Negate y2in based on sign LDP 2*16(b_ptr), (y0, y1) LDP 3*16(b_ptr), (y2, y3) MOVD $-1, acc0 SUBS y0, acc0, acc0 SBCS y1, const0, acc1 SBCS y2, ZR, acc2 SBCS y3, const1, acc3 SBC $0, ZR, t0 ADDS $-1, acc0, acc4 ADCS const0, acc1, acc5 ADCS $0, acc2, acc6 ADCS const1, acc3, acc7 ADC...