v0.Aux = symToAux(sym)
			v0.AddArg2(ptr, mem)
			return true
		}
		break
	}
	// match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a)
	// cond: a.Uses == 2 && a.Block == v.Block && clobber(a)
	// result: (TESTQ (MOVQload <a.Type> [off] {sym} ptr mem) x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			a := v_0
			if a.Op != OpAMD64ANDQload {

	TESTL R11, R11                          // 4585db
	TESTQ $-249346713, (BX)                 // 48f703674523f1
	TESTQ $-249346713, (R11)                // 49f703674523f1
	TESTQ $-249346713, DX                   // 48f7c2674523f1
	TESTQ $-249346713, R11                  // 49f7c3674523f1
	TESTQ DX, (BX)                          // 488513
	TESTQ R11, (BX)                         // 4c851b
	TESTQ DX, (R11)                         // 498513