v_0 := v.Args[0]
	b := v.Block
	// match: (MULW (NEG x) y)
	// result: (MNEGW x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != OpARM64NEG {
				continue
			}
			x := v_0.Args[0]
			y := v_1
			v.reset(OpARM64MNEGW)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (MULW x (MOVDconst [c]))
	// cond: int32(c)==-1

	MPSADBW $7, X2, X11                     // 66440f3a42da07
	MPSADBW $7, X11, X11                    // 66450f3a42db07
	MULW (BX)                               // 66f723
	MULW (R11)                              // 6641f723
	MULW DX                                 // 66f7e2
	MULW R11                                // 6641f7e3
	MULL (BX)                               // f723
	MULL (R11)                              // 41f723