v_0 := v.Args[0]
	b := v.Block
	// match: (SARL x (MOVQconst [c]))
	// result: (SARLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != OpAMD64MOVQconst {
			break
		}
		c := auxIntToInt64(v_1.AuxInt)
		v.reset(OpAMD64SARLconst)
		v.AuxInt = int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SARL x (MOVLconst [c]))
	// result: (SARLconst [int8(c&31)] x)

	SARL $1, (BX)                           // d13b
	SARL $1, (R11)                          // 41d13b
	SARL $1, DX                             // d1fa
	SARL $1, R11                            // 41d1fb
	SARL CL, (BX)                           // d33b
	SARL CL, (R11)                          // 41d33b
	SARL CL, DX                             // d3fa
	SARL CL, R11                            // 41d3fb

    `CUDA_ILLEGAL_ADDRESS` failures.

    Google discovered in mid-December 2017 that the PTX-to-SASS compiler in CUDA
    9 and CUDA 9.1 sometimes does not properly compute the carry bit when
    decomposing 64-bit address calculations with large offsets (e.g. `load [x +
    large_constant]`) into 32-bit arithmetic in SASS.

    As a result, these versions of `ptxas` miscompile most XLA programs which