// result: (Leq16U (RotateLeft16 <typ.UInt16> (Add16 <typ.UInt16> (Mul16 <typ.UInt16> (Const16 <typ.UInt16> [int16(sdivisible16(c).m)]) x) (Const16 <typ.UInt16> [int16(sdivisible16(c).a)]) ) (Const16 <typ.UInt16> [int16(16-sdivisible16(c).k)]) ) (Const16 <typ.UInt16> [int16(sdivisible16(c).max)]) )
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != OpMul16 {

		return true
	}
	// match: (CMPWconst (ANDLconst _ [m]) [n])
	// cond: 0 <= int16(m) && int16(m) < n
	// result: (FlagLT_ULT)
	for {
		n := auxIntToInt16(v.AuxInt)
		if v_0.Op != OpAMD64ANDLconst {
			break
		}
		m := auxIntToInt32(v_0.AuxInt)
		if !(0 <= int16(m) && int16(m) < n) {
			break
		}
		v.reset(OpAMD64FlagLT_ULT)
		return true
	}

pkg syscall (freebsd-arm64), type Flock_t struct, Start int64
pkg syscall (freebsd-arm64), type Flock_t struct, Sysid int32
pkg syscall (freebsd-arm64), type Flock_t struct, Type int16
pkg syscall (freebsd-arm64), type Flock_t struct, Whence int16
pkg syscall (freebsd-arm64), type Fsid struct
pkg syscall (freebsd-arm64), type Fsid struct, Val [2]int32
pkg syscall (freebsd-arm64), type ICMPv6Filter struct

    Arg<TensorOf<[TF_Int16, TF_Int32, TF_Int64]>, [{int16, int32 or int64, must be in the range `[-rank(input), rank(input))`.
Describes which dimension of the input Tensor to reduce across. For vectors,
use dimension = 0.}]>:$dimension
  );

  let results = (outs

pkg syscall (freebsd-riscv64), type Flock_t struct, Start int64 #53466
pkg syscall (freebsd-riscv64), type Flock_t struct, Sysid int32 #53466
pkg syscall (freebsd-riscv64), type Flock_t struct, Type int16 #53466
pkg syscall (freebsd-riscv64), type Flock_t struct, Whence int16 #53466
pkg syscall (freebsd-riscv64), type Fsid struct #53466
pkg syscall (freebsd-riscv64), type Fsid struct, Val [2]int32 #53466

		{"NullByte.Byte", Field, 17},
		{"NullByte.Valid", Field, 17},
		{"NullFloat64", Type, 0},
		{"NullFloat64.Float64", Field, 0},
		{"NullFloat64.Valid", Field, 0},
		{"NullInt16", Type, 17},
		{"NullInt16.Int16", Field, 17},
		{"NullInt16.Valid", Field, 17},
		{"NullInt32", Type, 13},
		{"NullInt32.Int32", Field, 13},
		{"NullInt32.Valid", Field, 13},
		{"NullInt64", Type, 0},
		{"NullInt64.Int64", Field, 0},

	v_0 := v.Args[0]
	// match: (MOVHreg (MOVDconst [c]))
	// result: (MOVDconst [int64(int16(c))])
	for {
		if v_0.Op != OpARM64MOVDconst {
			break
		}
		c := auxIntToInt64(v_0.AuxInt)
		v.reset(OpARM64MOVDconst)
		v.AuxInt = int64ToAuxInt(int64(int16(c)))
		return true
	}
	// match: (MOVHreg x)
	// cond: v.Type.Size() <= 2
	// result: x
	for {

    *   Added 16-bit and 32-bit int support for the built-in op `bitcast`.
    *   Added 8-bit/16-bit/32-bit int/uint support for the built-in op `bitwise_xor`
    *   Added int16 indices support for built-in op `gather` and `gather_nd`.
    *   Added 8-bit/16-bit/32-bit int/uint support for the built-in op `right_shift`
    *   Added reference implementation for 16-bit int unquantized `add`.