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Results 1 - 3 of 3 for sthx (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/ppc64.s

    	LVEWX (R3)(R4), V1              // 7c24188e
    	LVEWX (R3)(R0), V1              // 7c20188e
    	LVEWX (R3), V1                  // 7c20188e
    	STVX V1, (R3)(R4)               // 7c2419ce
    	STVX V1, (R3)(R0)               // 7c2019ce
    	STVX V1, (R3)                   // 7c2019ce
    	STVXL V1, (R3)(R4)              // 7c241bce
    	STVXL V1, (R3)(R0)              // 7c201bce
    	STVXL V1, (R3)                  // 7c201bce
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  2. gradle/verification-metadata.xml

             </artifact>
          </component>
          <component group="org.jvnet.staxex" name="stax-ex" version="1.8.1">
             <artifact name="stax-ex-1.8.1.jar">
                <pgp value="04543577D6A9CC626239C50C7ECBD740FF06AEB5"/>
             </artifact>
          </component>
          <component group="org.kamranzafar" name="jtar" version="2.3">
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Tue May 21 22:30:36 UTC 2024
    - 90.1K bytes
    - Viewed (0)
  3. src/crypto/internal/nistec/p256_asm_ppc64le.s

    // VSUBUQM, VSUBCUQ, and VSEL instructions.
    
    // 2. ppc64 does not have a multiply high and low
    // like s390x, so those were implemented using
    // macros to compute the equivalent values.
    
    // 3. The LVX, STVX instructions on ppc64 require
    // 16 byte alignment of the data.  To avoid that
    // requirement, data is loaded using LXVD2X and
    // STXVD2X with VPERM to reorder bytes correctly.
    
    // I have identified some areas where I believe
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 56.5K bytes
    - Viewed (0)
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