vector_one);
    auto slice_op =
        CreateSliceOpForTensorList(loc, /*input_list=*/input,
                                   /*start_index=*/scalar_zero, /*size=*/size,
                                   /*item_rank=*/partial_position_shape,
                                   /*result_type=*/result_type, rewriter);
    rewriter->create<func::ReturnOp>(loc, ArrayRef<Value>({slice_op}));
  }
};

	Map   map[string]Small
	MapP  map[string]*Small
	PMap  *map[string]Small
	PMapP *map[string]*Small

	EmptyMap map[string]Small
	NilMap   map[string]Small

	Slice   []Small
	SliceP  []*Small
	PSlice  *[]Small
	PSliceP *[]*Small

	EmptySlice []Small
	NilSlice   []Small

	StringSlice []string
	ByteSlice   []byte

	Small   Small
	PSmall  *Small

                       {
                           ConstOp::getOperationName(),
                           ReshapeOp::getOperationName(),
                           SliceOp::getOperationName(),
                           TransposeOp::getOperationName(),
                       }) {}

  LogicalResult matchAndRewrite(Operation *src_op,

		case OpSlicemask:
			// Replace OpSlicemask operations in b with constants where possible.
			x, delta := isConstDelta(v.Args[0])
			if x == nil {
				break
			}
			// slicemask(x + y)
			// if x is larger than -y (y is negative), then slicemask is -1.
			lim, ok := ft.limits[x.ID]
			if !ok {
				break
			}
			if lim.umin > uint64(-delta) {
				if v.Args[0].Op == OpAdd64 {
					v.reset(OpConst64)

  (replaceWithValue $input),
  [(CanOptimizeIdentitySliceOp $input, $begin, $size)]>;

// Convert the StridedSliceOp to a SliceOp when possible. This will enable other
// optimizations on SliceOp to run.
def OptimizeStridedSlice : Pat<
  (TFL_StridedSliceOp $input,
    (Arith_ConstantOp $begin),
    (Arith_ConstantOp $end),
    (Arith_ConstantOp $stride),

(ZeroExt8to32  ...) => (MOVBQZX ...)
(ZeroExt8to64  ...) => (MOVBQZX ...)
(ZeroExt16to32 ...) => (MOVWQZX ...)
(ZeroExt16to64 ...) => (MOVWQZX ...)
(ZeroExt32to64 ...) => (MOVLQZX ...)

(Slicemask <t> x) => (SARQconst (NEGQ <t> x) [63])

(SpectreIndex <t> x y) => (CMOVQCC x (MOVQconst [0]) (CMPQ x y))
(SpectreSliceIndex <t> x y) => (CMOVQHI x (MOVQconst [0]) (CMPQ x y))

// Lowering truncation

(AtomicCompareAndSwapRel32   ptr old new_ mem) => (LoweredAtomicCas32 [0] ptr old new_ mem)

(AtomicAnd(8|32)  ...) => (LoweredAtomicAnd(8|32)  ...)
(AtomicOr(8|32)   ...) => (LoweredAtomicOr(8|32)   ...)

(Slicemask <t> x) => (SRADconst (NEG <t> x) [63])
(ANDconst [1] z:(SRADconst [63] x)) && z.Uses == 1  => (SRDconst [63] x)

// Note that MOV??reg returns a 64-bit int, x is not necessarily that wide

(SignExt16to(32|64) ...) => (MOVHreg ...)
(SignExt32to64 ...) => (MOVWreg ...)

(ZeroExt8to(16|32|64) ...) => (MOVBZreg ...)
(ZeroExt16to(32|64) ...) => (MOVHZreg ...)
(ZeroExt32to64 ...) => (MOVWZreg ...)

(Slicemask <t> x) => (SRADconst (NEG <t> x) [63])

// Lowering truncation
// Because we ignore high parts of registers, truncates are just copies.
(Trunc(16|32|64)to8 ...) => (Copy ...)
(Trunc(32|64)to16 ...) => (Copy ...)

(SignExt8to32 ...) => (MOVBreg ...)
(SignExt16to32 ...) => (MOVHreg ...)

(Signmask x) => (SRAconst x [31])
(Zeromask x) => (SRAconst (RSBshiftRL <typ.Int32> x x [1]) [31]) // sign bit of uint32(x)>>1 - x
(Slicemask <t> x) => (SRAconst (RSBconst <t> [0] x) [31])

// float <-> int conversion
(Cvt32to32F ...) => (MOVWF ...)
(Cvt32to64F ...) => (MOVWD ...)
(Cvt32Uto32F ...) => (MOVWUF ...)
(Cvt32Uto64F ...) => (MOVWUD ...)