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Results 1 - 4 of 4 for mulldo (0.37 sec)

  1. src/cmd/asm/internal/asm/testdata/ppc64.s

    	MULLD $20, R4                   // 1c840014
    	MULLD $200000000, R4            // 641f0beb63ffc2007c9f21d2
    
    	MULLDCC R3, R4, R5              // 7ca419d3
    	MULHD R3, R4, R5                // 7ca41892
    	MULHDCC R3, R4, R5              // 7ca41893
    	MULHDU R3, R4, R5               // 7ca41812
    	MULHDUCC R3, R4, R5             // 7ca41813
    
    	MULLWV R3, R4                   // 7c841dd6
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/S390XOps.go

    		{name: "MULLWload", argLength: 3, reg: gpopload, asm: "MULLW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 * *arg1. arg2=mem
    
    		{name: "MULHD", argLength: 2, reg: gp21tmp, asm: "MULHD", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true},   // (arg0 * arg1) >> width
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 52.5K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
    
    (Mul64 ...) => (MULLD ...)
    (Mul(32|16|8) ...) => (MULLW ...)
    (Select0 (Mul64uhilo x y)) => (MULHDU x y)
    (Select1 (Mul64uhilo x y)) => (MULLD x y)
    
    (Div64 [false] x y) => (DIVD x y)
    (Div64u ...) => (DIVDU ...)
    (Div32 [false] x y) => (DIVW x y)
    (Div32u ...) => (DIVWU ...)
    (Div16 [false]  x y) => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/S390X.rules

    // TODO(mundaym): indexed versions of these?
    ((ADD|SUB|MULLD|AND|OR|XOR) <t> x g:(MOVDload [off] {sym} ptr mem))
      && ptr.Op != OpSB
      && is20Bit(int64(off))
      && canMergeLoadClobber(v, g, x)
      && clobber(g)
      => ((ADD|SUB|MULLD|AND|OR|XOR)load <t> [off] {sym} x ptr mem)
    ((ADD|SUB|MULL|AND|OR|XOR)W <t> x g:(MOVWload [off] {sym} ptr mem))
      && ptr.Op != OpSB
      && is20Bit(int64(off))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
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