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Results 1 - 10 of 25 for dmul (0.05 sec)
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src/cmd/compile/internal/ssa/_gen/AMD64.rules
(Sub(32|64)F ...) => (SUBS(S|D) ...) (Mul(64|32|16|8) ...) => (MUL(Q|L|L|L) ...) (Mul(32|64)F ...) => (MULS(S|D) ...) (Select0 (Mul64uover x y)) => (Select0 <typ.UInt64> (MULQU x y)) (Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y)) (Select1 (Mul(64|32)uover x y)) => (SETO (Select1 <types.TypeFlags> (MUL(Q|L)U x y))) (Hmul(64|32) ...) => (HMUL(Q|L) ...) (Hmul(64|32)u ...) => (HMUL(Q|L)U ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_ppc64le.s
// X=Z1; Y=Z1; MUL; T- // T1 = Z1*Z1 // X- ; Y=T ; MUL; R=T // R = Z1*T1 // X=X2; Y- ; MUL; H=T // H = X2*T1 // X=Z2; Y=Z2; MUL; T- // T2 = Z2*Z2 // X- ; Y=T ; MUL; S1=T // S1 = Z2*T2 // X=X1; Y- ; MUL; U1=T // U1 = X1*T2 // SUB(H<H-T) // H = H-U1 // X=Z1; Y=Z2; MUL; T- // Z3 = Z1*Z2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 56.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/replace_cast_hacks_with_tf_xla_ops.mlir
%5 = "tf.AddV2"(%4, %arg2) : (tensor<1x3x2x2xi32>, tensor<2xi32>) -> tensor<1x3x2x2xi32> %6 = "tf.Mul"(%arg3, %arg5) : (tensor<f32>, tensor<f32>) -> tensor<f32> %7 = "tf.Div"(%6, %arg9) : (tensor<f32>, tensor<f32>) -> tensor<f32> %8 = "tf.Cast"(%5) {Truncate = false} : (tensor<1x3x2x2xi32>) -> tensor<1x3x2x2xf32> %9 = "tf.Mul"(%7, %8) : (tensor<f32>, tensor<1x3x2x2xf32>) -> tensor<1x3x2x2xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 81K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(MOVWnop (MOVWconst [c])) => (MOVWconst [c]) // mul by constant (MUL x (MOVWconst [c])) && int32(c) == -1 => (RSBconst [0] x) (MUL _ (MOVWconst [0])) => (MOVWconst [0]) (MUL x (MOVWconst [1])) => x (MUL x (MOVWconst [c])) && isPowerOfTwo32(c) => (SLLconst [int32(log32(c))] x) (MUL x (MOVWconst [c])) && isPowerOfTwo32(c-1) && c >= 3 => (ADDshiftLL x x [int32(log32(c-1))])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/math/big/int_test.go
} } func checkGcd(aBytes, bBytes []byte) bool { x := new(Int) y := new(Int) a := new(Int).SetBytes(aBytes) b := new(Int).SetBytes(bBytes) d := new(Int).GCD(x, y, a, b) x.Mul(x, a) y.Mul(y, b) x.Add(x, y) return x.Cmp(d) == 0 } // euclidExtGCD is a reference implementation of Euclid's // extended GCD algorithm for testing against optimized algorithms. // Requirements: a, b > 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 18:42:28 UTC 2024 - 58.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-tf.mlir
// scale * rsqrt(variance + epsilon) // CHECK: %[[MUL1:.*]] = "tf.Mul"(%[[ARG1:.*]], %[[RSQRT]]) // x * scale * rsqrt(variance + epsilon) // CHECK: %[[MUL2:.*]] = "tf.Mul"(%[[ARG0:.*]], %[[MUL1]]) // mean * scale * rsqrt(variance + epsilon) // CHECK: %[[MUL3:.*]] = "tf.Mul"(%[[ARG3:.*]], %[[MUL1]]) // offset - mean * scale * rsqrt(variance + epsilon)
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 29 07:26:59 UTC 2024 - 59.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/tests/raise-target-subgraphs.mlir
%0 = "tfl.add"(%arg0, %arg1) {tac.device = "GPU", fused_activation_function = "RELU6", tac.inference_type = "FLOAT"} : (tensor<1xf32>, tensor<1xf32>) -> tensor<1xf32> %1 = "tfl.mul"(%0, %arg2) {tac.device = "GPU", fused_activation_function = "RELU6", tac.inference_type = "FLOAT"} : (tensor<1xf32>, tensor<1xf32>) -> tensor<1xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 74.9K bytes - Viewed (0) -
src/cmd/internal/obj/mips/asm0.go
{AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0, sys.MIPS64, 0}, {AMOVW, C_REG, C_NONE, C_LO, 21, 4, 0, 0, 0}, {AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0, sys.MIPS64, 0}, {AMUL, C_REG, C_REG, C_NONE, 22, 4, 0, 0, 0}, {AMUL, C_REG, C_REG, C_REG, 22, 4, 0, 0, 0}, {AMULV, C_REG, C_REG, C_NONE, 22, 4, 0, sys.MIPS64, 0}, {AADD, C_ADD0CON, C_REG, C_REG, 4, 4, 0, 0, 0}, {AADD, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
MULALU R1, R2, (R4, R3) // 9231a4e0 MULALU.S R1, R2, (R4, R3) // 9231b4e0 // MUL MUL R2, R3, R4 // 930204e0 MUL R2, R4 // 940204e0 MUL R2, R4, R4 // 940204e0 MUL.S R2, R3, R4 // 930214e0 MUL.S R2, R4 // 940214e0 MUL.S R2, R4, R4 // 940214e0 MULU R5, R6, R7 // 960507e0 MULU R5, R7 // 970507e0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/go/parser/parser.go
name, typ = p.parseArrayFieldOrTypeInstance(name) if name == nil { names = nil } } else { // T P typ = p.parseType() } } case token.MUL: star := p.pos p.next() if p.tok == token.LPAREN { // *(T) p.error(p.pos, "cannot parenthesize embedded type") p.next() typ = p.parseQualifiedIdent(nil)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 08 20:07:50 UTC 2023 - 72.2K bytes - Viewed (0)