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Results 1 - 6 of 6 for divwe (0.06 sec)
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src/cmd/asm/internal/asm/testdata/ppc64.s
DIVD R3, R4, R5 // 7ca41bd2 DIVW R3, R4 // 7c841bd6 DIVW R3, R4, R5 // 7ca41bd6 DIVDCC R3,R4, R5 // 7ca41bd3 DIVWCC R3,R4, R5 // 7ca41bd7 DIVDU R3, R4, R5 // 7ca41b92 DIVWU R3, R4, R5 // 7ca41b96 DIVDV R3, R4, R5 // 7ca41fd2 DIVWV R3, R4, R5 // 7ca41fd6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Div64 [false] x y) => (DIVD x y) (Div64u ...) => (DIVDU ...) (Div32 [false] x y) => (DIVW x y) (Div32u ...) => (DIVWU ...) (Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y)) (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y)) (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) (Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Div64u ...) => (DIVDU ...) // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor, // so a sign/zero extension of the dividend is required. (Div32 x y) => (DIVW (MOVWreg x) y) (Div32u x y) => (DIVWU (MOVWZreg x) y) (Div16 x y) => (DIVW (MOVHreg x) (MOVHreg y)) (Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y)) (Div8 x y) => (DIVW (MOVBreg x) (MOVBreg y)) (Div8u x y) => (DIVWU (MOVBZreg x) (MOVBZreg y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
{name: "DIVW", argLength: 2, reg: gp21tmp, asm: "DIVW", resultInArg0: true, clobberFlags: true}, // arg0 / arg1 {name: "DIVDU", argLength: 2, reg: gp21tmp, asm: "DIVDU", resultInArg0: true, clobberFlags: true}, // arg0 / arg1 {name: "DIVWU", argLength: 2, reg: gp21tmp, asm: "DIVWU", resultInArg0: true, clobberFlags: true}, // arg0 / arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(Hmul(64|32) ...) => (HMUL(Q|L) ...) (Hmul(64|32)u ...) => (HMUL(Q|L)U ...) (Div(64|32|16) [a] x y) => (Select0 (DIV(Q|L|W) [a] x y)) (Div8 x y) => (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) (Div(64|32|16)u x y) => (Select0 (DIV(Q|L|W)U x y)) (Div8u x y) => (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) (Div(32|64)F ...) => (DIVS(S|D) ...) (Select0 (Add64carry x y c)) =>
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0)