DIVWVCC R3, R4, R5              // 7ca41fd7
	DIVDUV R3, R4, R5               // 7ca41f92
	DIVDUVCC R3, R4, R5             // 7ca41f93
	DIVWUVCC R3, R4, R5             // 7ca41f97
	DIVWUV   R3, R4, R5             // 7ca41f96
	DIVDE R3, R4, R5                // 7ca41b52
	DIVDECC R3, R4, R5              // 7ca41b53
	DIVDEU R3, R4, R5               // 7ca41b12
	DIVDEUCC R3, R4, R5             // 7ca41b13

		{name: "DIVW", argLength: 2, reg: gp21tmp, asm: "DIVW", resultInArg0: true, clobberFlags: true},   // arg0 / arg1
		{name: "DIVDU", argLength: 2, reg: gp21tmp, asm: "DIVDU", resultInArg0: true, clobberFlags: true}, // arg0 / arg1
		{name: "DIVWU", argLength: 2, reg: gp21tmp, asm: "DIVWU", resultInArg0: true, clobberFlags: true}, // arg0 / arg1

(Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y)
(Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y)))
(Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y)
(Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y)))
(Mod32 x y) && buildcfg.GOPPC64 >= 9 => (MODSW x y)
(Mod32 x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVW x y)))
(Mod32u x y) && buildcfg.GOPPC64 >= 9 => (MODUW x y)

(Mul(32|16|8) ...) => (MULLW ...)
(Mul32F ...) => (FMULS ...)
(Mul64F ...) => (FMUL ...)
(Mul64uhilo ...) => (MLGR ...)

(Div32F ...) => (FDIVS ...)
(Div64F ...) => (FDIV ...)

(Div64 x y) => (DIVD x y)
(Div64u ...) => (DIVDU ...)
// DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
// so a sign/zero extension of the dividend is required.
(Div32  x y) => (DIVW  (MOVWreg x) y)
(Div32u x y) => (DIVWU (MOVWZreg x) y)