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Results 1 - 6 of 6 for cmpb (2.36 sec)
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src/runtime/asm_amd64.s
MOVQ SP, (g_stack+stack_hi)(DI) // find out information about the processor we're on MOVL $0, AX CPUID CMPL AX, $0 JE nocpuinfo CMPL BX, $0x756E6547 // "Genu" JNE notintel CMPL DX, $0x49656E69 // "ineI" JNE notintel CMPL CX, $0x6C65746E // "ntel" JNE notintel MOVB $1, runtime·isIntel(SB) notintel: // Load EAX=1 cpuid flags MOVL $1, AX CPUID
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 60.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
// Fold boolean tests into blocks (NE (TESTB (SETL cmp) (SETL cmp)) yes no) => (LT cmp yes no) (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) => (LE cmp yes no) (NE (TESTB (SETG cmp) (SETG cmp)) yes no) => (GT cmp yes no) (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) => (GE cmp yes no) (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) => (EQ cmp yes no) (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) => (NE cmp yes no)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
// TODO: cleanup inconsistency of printing CMPx opcodes with explicit CR arguments. CMP R3, R4 // 7c232000 CMP R3, R0 // 7c230000 CMP R3, R0, CR1 // CMP R3,CR1,R0 // 7ca30000 CMPU R3, R4 // 7c232040 CMPU R3, R0 // 7c230040 CMPU R3, R0, CR2 // CMPU R3,CR2,R0 // 7d230040 CMPW R3, R4 // 7c032000
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfr/python/tfr_gen.py
'\n{} = tfr.equal {}, {} -> i1'.format(ret, lhs, rhs), node) else: if lhs_ty == TFRTypes.I64: code = 'arith.cmpi' elif lhs_ty == TFRTypes.F32: code = 'arith.cmpf' elif lhs_ty == TFRTypes.INDEX: code = 'arith.cmpi' # TODO(fengliuai): the reverse type inference should solve the issue. rhs, _ = self._i64_to_index(rhs, rhs_ty) else:
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Apr 27 15:27:03 UTC 2022 - 55.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
// before its corresponding VarDef. // See issue 28445. // v1 = LOAD ... // v2 = VARDEF // v3 = LEAQ // v4 = CMPQ v1 v3 // We don't want to combine the CMPQ with the load, because // that would force the CMPQ to schedule before the VARDEF, which // in turn requires the LEAQ to schedule before the VARDEF. return false } if v.Type.IsMemory() {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
&& int32(x) != 0 => (BRC {d} cmp yes no) // Canonicalize BRC condition code mask by removing impossible conditions. // Integer comparisons cannot generate the unordered condition. (BRC {c} x:((CMP|CMPW|CMPU|CMPWU) _ _) yes no) && c&s390x.Unordered != 0 => (BRC {c&^s390x.Unordered} x yes no)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0)