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src/cmd/compile/internal/ssa/rewrite.go
} // returns the lsb part of the auxInt field of arm64 bitfield ops. func (bfc arm64BitField) getARM64BFlsb() int64 { return int64(uint64(bfc) >> 8) } // returns the width part of the auxInt field of arm64 bitfield ops. func (bfc arm64BitField) getARM64BFwidth() int64 { return int64(bfc) & 0xff } // checks if mask >> rshift applied at lsb is a valid arm64 bitfield op mask.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
SWI $65535 // ffff00ef SWI // 000000ef // BFX/BFXU/BFC/BFI BFX $16, $8, R1, R2 // BFX $16, R1, $8, R2 // 5124afe7 BFX $29, $2, R8 // 5881bce7 BFXU $16, $8, R1, R2 // BFXU $16, R1, $8, R2 // 5124efe7 BFXU $29, $2, R8 // 5881fce7 BFC $29, $2, R8 // 1f81dee7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
r := int(p.Reg) o1 |= (uint32(rf)&15)<<8 | (uint32(r)&15)<<0 | (uint32(rt)&15)<<16 | (uint32(rt2)&15)<<12 case 18: /* BFX/BFXU/BFC/BFI */ o1 = c.oprrr(p, p.As, int(p.Scond)) rt := int(p.To.Reg) r := int(p.Reg) if r == 0 { r = rt } else if p.As == ABFC { // only "BFC $width, $lsb, Reg" is accepted, p.Reg must be 0 c.ctxt.Diag("illegal combination: %v", p) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0)