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Results 1 - 5 of 5 for ULE (0.39 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (ULT (FlagConstant [fc]) yes no) &&  fc.ult() => (First yes no)
    (ULT (FlagConstant [fc]) yes no) && !fc.ult() => (First no yes)
    
    (ULE (FlagConstant [fc]) yes no) &&  fc.ule() => (First yes no)
    (ULE (FlagConstant [fc]) yes no) && !fc.ule() => (First no yes)
    
    (UGT (FlagConstant [fc]) yes no) &&  fc.ugt() => (First yes no)
    (UGT (FlagConstant [fc]) yes no) && !fc.ugt() => (First no yes)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    ((EQ|LE|GE|ULE|UGE) (FlagEQ) yes no)     => (First yes no)
    ((NE|LT|GT|ULT|UGT) (FlagEQ) yes no)     => (First no yes)
    ((NE|LT|LE|ULT|ULE) (FlagLT_ULT) yes no) => (First yes no)
    ((EQ|GT|GE|UGT|UGE) (FlagLT_ULT) yes no) => (First no yes)
    ((NE|LT|LE|UGT|UGE) (FlagLT_UGT) yes no) => (First yes no)
    ((EQ|GT|GE|ULT|ULE) (FlagLT_UGT) yes no) => (First no yes)
    ((NE|GT|GE|ULT|ULE) (FlagGT_ULT) yes no) => (First yes no)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/rewrite.go

    	case OpARM64GreaterThan:
    		return b2i(fc.gt())
    	case OpARM64GreaterThanU:
    		return b2i(fc.ugt())
    	case OpARM64LessEqual:
    		return b2i(fc.le())
    	case OpARM64LessEqualU:
    		return b2i(fc.ule())
    	case OpARM64GreaterEqual:
    		return b2i(fc.ge())
    	case OpARM64GreaterEqualU:
    		return b2i(fc.uge())
    	}
    	return 0
    }
    
    // logRule logs the use of the rule s. This will only be enabled if
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 64.2K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tfr/python/tfr_gen.py

          rhs, rhs_ty = self.visit(right)
          if isinstance(op, ast.Eq):
            pred = 'eq'
          elif isinstance(op, ast.Lt):
            pred = 'ult'
          elif isinstance(op, ast.LtE):
            pred = 'ule'
          elif isinstance(op, ast.Gt):
            pred = 'ugt'
          elif isinstance(op, ast.GtE):
            pred = 'uge'
          elif isinstance(op, ast.NotEq):
            pred = 'ne'
          else:
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Apr 27 15:27:03 UTC 2022
    - 55.8K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "NE", controls: 1},
    		{name: "LT", controls: 1},
    		{name: "LE", controls: 1},
    		{name: "GT", controls: 1},
    		{name: "GE", controls: 1},
    		{name: "ULT", controls: 1},
    		{name: "ULE", controls: 1},
    		{name: "UGT", controls: 1},
    		{name: "UGE", controls: 1},
    		{name: "Z", controls: 1},                  // Control == 0 (take a register instead of flags)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
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