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Results 1 - 3 of 3 for RSB (0.02 sec)

  1. src/cmd/asm/internal/asm/testdata/arm.s

    	RSB	R0->28, R1           // 401e61e0
    	RSB	R0@>28, R1           // 601e61e0
    	RSB.S	R0<<28, R1           // 001e71e0
    	RSB.S	R0>>28, R1           // 201e71e0
    	RSB.S	R0->28, R1           // 401e71e0
    	RSB.S	R0@>28, R1           // 601e71e0
    	RSB	R0<<R1, R2, R3       // 103162e0
    	RSB	R0>>R1, R2, R3       // 303162e0
    	RSB	R0->R1, R2, R3       // 503162e0
    	RSB	R0@>R1, R2, R3       // 703162e0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (SUBS (SRA y z) x) => (RSBSshiftRAreg x y z)
    (RSB x (SLLconst [c] y)) => (RSBshiftLL x y [c])
    (RSB (SLLconst [c] y) x) => (SUBshiftLL x y [c])
    (RSB x (SRLconst [c] y)) => (RSBshiftRL x y [c])
    (RSB (SRLconst [c] y) x) => (SUBshiftRL x y [c])
    (RSB x (SRAconst [c] y)) => (RSBshiftRA x y [c])
    (RSB (SRAconst [c] y) x) => (SUBshiftRA x y [c])
    (RSB x (SLL y z)) => (RSBshiftLLreg x y z)
    (RSB (SLL y z) x) => (SUBshiftLLreg x y z)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/arm/asm5.go

    			r = rt
    		}
    		x, y := immrot2a(uint32(c.instoffset))
    		var as2 obj.As
    		switch p.As {
    		case AADD, ASUB, AORR, AEOR, ABIC:
    			as2 = p.As // ADD, SUB, ORR, EOR, BIC
    		case ARSB:
    			as2 = AADD // RSB -> RSB/ADD pair
    		case AADC:
    			as2 = AADD // ADC -> ADC/ADD pair
    		case ASBC:
    			as2 = ASUB // SBC -> SBC/SUB pair
    		case ARSC:
    			as2 = AADD // RSC -> RSC/ADD pair
    		default:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 79.4K bytes
    - Viewed (0)
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