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Results 1 - 3 of 3 for OpSelect0 (0.18 sec)

  1. src/cmd/compile/internal/ssa/rewrite.go

    		// most other architectures load them sign/zero extended based on the type.
    		return x.Type.Size() == 4 && (x.Type.IsUnsigned() || x.Block.Func.Config.arch == "amd64")
    	case OpPhi, OpSelect0, OpSelect1:
    		// Phis can use each-other as an arguments, instead of tracking visited values,
    		// just limit recursion depth.
    		if depth <= 0 {
    			return false
    		}
    		for i := range x.Args {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 64.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewritedec64.go

    		v5.AddArg(x)
    		v6 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
    		v6.AddArg(y)
    		v4.AddArg2(v5, v6)
    		v3.AddArg(v4)
    		v0.AddArg3(v1, v2, v3)
    		v7 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32)
    		v7.AddArg(v4)
    		v.AddArg2(v0, v7)
    		return true
    	}
    }
    func rewriteValuedec64_OpAnd64(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jan 19 22:42:34 UTC 2023
    - 65.3K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/regalloc.go

    					continue
    				}
    				desired.clobber(j.regs)
    				desired.add(v.Args[j.idx].ID, pickReg(j.regs))
    			}
    			if opcodeTable[v.Op].resultInArg0 || v.Op == OpAMD64ADDQconst || v.Op == OpAMD64ADDLconst || v.Op == OpSelect0 {
    				if opcodeTable[v.Op].commutative {
    					desired.addList(v.Args[1].ID, prefs)
    				}
    				desired.addList(v.Args[0].ID, prefs)
    			}
    			// Save desired registers for this value.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 17:49:56 UTC 2023
    - 87.2K bytes
    - Viewed (0)
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